From 7a8a30862054feb5f78b5b617c52213a3805ed23 Mon Sep 17 00:00:00 2001 From: Priec Date: Tue, 18 Nov 2025 23:23:33 +0100 Subject: [PATCH] now im reading proper buffer --- semestralka_1d_rx_bez_dma/src/bin/main.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/semestralka_1d_rx_bez_dma/src/bin/main.rs b/semestralka_1d_rx_bez_dma/src/bin/main.rs index d7a02dc..56fc232 100644 --- a/semestralka_1d_rx_bez_dma/src/bin/main.rs +++ b/semestralka_1d_rx_bez_dma/src/bin/main.rs @@ -155,7 +155,7 @@ pub async fn bridge_usart1_rx_to_usart2_tx( let n = usart1_rx.read(&mut buf).await; if n > 0 { let _ = usart2_tx.write(&buf[..n]).await; - // info!("bridge: USART1 -> USART2 sent {} bytes", n); + info!("Buffer USART1 -> USART2 bytes: {:?}", &buf[..n]); } yield_now().await; } @@ -171,7 +171,7 @@ pub async fn bridge_usart2_rx_to_usart1_tx( let n = usart2_rx.read(&mut buf).await; if n > 0 { let _ = usart1_tx.write(&buf[..n]).await; - info!("Buffer USART2 -> USART1 bytes: {:?}", &buf[..n]); + // info!("Buffer USART2 -> USART1 bytes: {:?}", &buf[..n]); } yield_now().await; }