filipriec/stm32_rust
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jsut minor changes, UNTESTED DMA TIMER CHANGE

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Priec
2025-11-20 13:28:09 +01:00
parent 179bec6ed6
commit 685067a75f
5 changed files with 21 additions and 26 deletions
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11
semestralka_1_connected/src/bin/main.rs
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@@ -68,11 +68,11 @@ async fn main(spawner: Spawner) {
config.rcc.pll1 = Some(Pll {
source: PllSource::HSI,
// 16 MHz / 1 × 20 / 2 = 160 MHz
prediv: PllPreDiv::DIV1, // or 1.into()
mul: PllMul::MUL20, // or 20.into()
prediv: PllPreDiv::DIV1,
mul: PllMul::MUL20,
divp: None,
divq: None,
divr: Some(PllDiv::DIV2), // or Some(2.into())
divr: Some(PllDiv::DIV2),
});
config.enable_independent_io_supply = true;
config.enable_independent_analog_supply = true;
@@ -131,14 +131,12 @@ async fn main(spawner: Spawner) {
let rx_pin = Input::new(p.PD6, Pull::Up);
unsafe { RX_PIN = Some(rx_pin) };
// Configure TX as output (PB0)
let mut tx_pin = Output::new(p.PB0, Level::High, Speed::VeryHigh);
init_tim6_for_uart(p.TIM6, BAUD, TX_OVERSAMPLE);
init_tim7_for_uart(p.TIM7, BAUD, RX_OVERSAMPLE);
dump_tim6_regs();
let bsrr_ptr = embassy_stm32::pac::GPIOB.bsrr().as_ptr() as *mut u32; // POZOR B REGISTER
let bsrr_ptr = embassy_stm32::pac::GPIOB.bsrr().as_ptr() as *mut u32; // POZOR B REGISTER
spawner.spawn(tx_dma_task(p.GPDMA1_CH0, bsrr_ptr, SW_TX_RING.init([0; TX_RING_BYTES]), &PIPE_SW_TX).unwrap());
// EDN OF SOFTWARE UART
@@ -148,7 +146,6 @@ async fn main(spawner: Spawner) {
spawner.spawn(rx_dma_task(p.GPDMA1_CH1, gpio_idr, rx_ring, &PIPE_SW_RX).unwrap());
info!("SW UART RX DMA started");
// Process decoded bytes coming from PIPE_SW_RX
let mut buf = [0u8; 64];
loop {
let n = PIPE_SW_RX.read(&mut buf).await;