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working write immidiate

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This commit is contained in:
Priec
2025-11-07 21:23:31 +01:00
parent f2fda10c7a
commit 6620f9ad2b
3 changed files with 114 additions and 52 deletions
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136
dma_gpio2/src/bin/main.rs
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@@ -7,7 +7,6 @@ use embassy_executor::Spawner;
use embassy_futures::yield_now;
use embassy_stm32::dma::Request;
use embassy_stm32::gpio::{Input, Output, Level, Pull, Speed};
use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
use embassy_time::{Duration, Timer};
use embassy_stm32::dma::{TransferOptions, WritableRingBuffer};
use dma_gpio::software_uart::{
@@ -15,57 +14,59 @@ use dma_gpio::software_uart::{
gpio_dma_uart_tx::encode_uart_frames,
debug::dump_tim6_regs,
};
use dma_gpio::config::{BAUD, TX_PIN_BIT, RX_OVERSAMPLE, TX_OVERSAMPLE};
use dma_gpio::config::{TX_RING_BYTES, RX_RING_BYTES, PIPE_RX_SIZE};
use dma_gpio::config::{BAUD, TX_PIN_BIT, TX_OVERSAMPLE, TX_RING_BYTES};
use static_cell::StaticCell;
use {defmt_rtt as _, panic_probe as _};
// kapitola 17.4.11 - 2 casovace pre 2 DMA
pub const TIM6_UP_REQ: Request = 4; // Table 137: tim6_upd_dma, strana 687 STM32U5xx datasheet
pub const TIM6_UP_REQ: Request = 4;
static TX_RING: StaticCell<[u32; TX_RING_BYTES]> = StaticCell::new();
use core::future::poll_fn;
use core::task::Poll;
async fn wait_for_space<'a, W: embassy_stm32::dma::word::Word>(
ring: &mut embassy_stm32::dma::WritableRingBuffer<'a, W>,
min_free: usize,
// Wait until there is at least `needed` free space in the TX ring.
async fn wait_for_space<'a>(
ring: &mut WritableRingBuffer<'a, u32>,
needed: usize,
) {
poll_fn(|cx| {
let used = ring.len().unwrap_or(0);
let cap = ring.capacity();
if cap - used > min_free {
let used = ring.len().unwrap_or(0);
let free = cap.saturating_sub(used);
if free >= needed {
Poll::Ready(())
} else {
ring.set_waker(cx.waker());
Poll::Pending
}
}).await
})
.await
}
#[embassy_executor::main]
async fn main(spawner: Spawner) {
async fn main(_spawner: Spawner) {
let p = embassy_stm32::init(Default::default());
info!("Hehe");
let _rx = Input::new(p.PA3, Pull::Up);
let _rx = Input::new(p.PA3, embassy_stm32::gpio::Pull::Up);
let _tx = Output::new(p.PA2, Level::High, Speed::VeryHigh);
init_tim6_for_uart(p.TIM6, BAUD, TX_OVERSAMPLE);
dump_tim6_regs();
// Safe one-time init from StaticCell
let tx_ring_mem: &mut [u32; TX_RING_BYTES] = TX_RING.init([0; TX_RING_BYTES]);
let idle: u32 = 1u32 << TX_PIN_BIT;
// Ring initialized to idle (line high).
let tx_ring_mem: &mut [u32; TX_RING_BYTES] = TX_RING.init([idle; TX_RING_BYTES]);
// Create and start the TX DMA ring in main.
// let bsrr_ptr = embassy_stm32::pac::GPIOA.bsrr().as_ptr() as *mut u32;
let odr_ptr = embassy_stm32::pac::GPIOA.odr().as_ptr() as *mut u32;
let mut tx_opts = TransferOptions::default();
tx_opts.half_transfer_ir = true;
tx_opts.complete_transfer_ir = true;
// SAFETY: tx_ring_mem is exclusive
let mut tx_ring = unsafe {
WritableRingBuffer::new(
p.GPDMA1_CH0,
@@ -75,9 +76,45 @@ async fn main(spawner: Spawner) {
tx_opts,
)
};
// Start DMA
tx_ring.start();
info!("TX DMA ring started");
info!(
"TX DMA ring started: cap_words={}",
tx_ring.capacity()
);
unsafe {
use embassy_stm32::pac::gpdma::Gpdma;
let dma = Gpdma::from_ptr(0x4002_0000 as _); // GPDMA1 base for STM32U5
let ch = dma.ch(0); // Channel 0
let cr = ch.cr().read();
let tr1 = ch.tr1().read();
let tr2 = ch.tr2().read();
let br1 = ch.br1().read();
let sar = ch.sar().read();
let dar = ch.dar().read();
let llr = ch.llr().read();
let lbar = ch.lbar().read();
info!(
"GPDMA1_CH0: EN={} HTIE={} TCIE={} SDW={:?} DDW={:?} SINC={} DINC={} BNDT={} SAR=0x{:08x} DAR=0x{:08x}",
cr.en(),
cr.htie(),
cr.tcie(),
tr1.sdw(),
tr1.ddw(),
tr1.sinc(),
tr1.dinc(),
br1.bndt(),
sar, // already u32
dar, // already u32
);
info!(
"GPDMA1_CH0: LBAR=0x{:08x} LLR=0x{:08x}",
lbar.lba(),
llr.0
);
}
let mut frame_buf = [0u32; 4096];
@@ -86,17 +123,58 @@ async fn main(spawner: Spawner) {
Timer::after(Duration::from_millis(400)).await;
info!("tick end");
let used = encode_uart_frames(TX_PIN_BIT, b"Hello marshmallow\r\n", &mut frame_buf).await;
// Wait for DMA to free space, async style
wait_for_space(&mut tx_ring, used / 2).await;
if let Err(e) = tx_ring.write_exact(&frame_buf[..used]).await {
warn!("DMA ring write error: {:?}", e);
} else {
info!("Frame queued to DMA ring");
// Prepare scratch buffer with idle.
for w in frame_buf.iter_mut() {
*w = idle;
}
let used = encode_uart_frames(
TX_PIN_BIT,
b"Hello marshmallow\r\n",
&mut frame_buf,
)
.await;
if used == 0 {
info!("encode_uart_frames() produced 0 words, skipping write");
yield_now().await;
continue;
}
// Debug: confirm encoded content.
let preview = core::cmp::min(used, 32);
info!(
"TX frame used={} words, head={=[?]}",
used,
&frame_buf[..preview]
);
// Wait until the ring has room for this frame.
wait_for_space(&mut tx_ring, used).await;
// Now it is safe to call write_exact.
match tx_ring.write_immediate(&frame_buf[..used]) {
Ok((written, remaining)) => {
let len = tx_ring.len().unwrap_or(0);
info!(
"write_immediate ok: written={} remaining={} ring_used={} ring_cap={}",
written,
remaining,
len,
tx_ring.capacity()
);
}
Err(e) => {
let len = tx_ring.len().unwrap_or(0);
warn!(
"write_immediate error: {:?}, ring_used={} ring_cap={}",
e,
len,
tx_ring.capacity()
);
}
}
yield_now().await;
}
}