working but probably wrong. timer + bit turn on for semestralka1

semestralka_1/src/bin/main.rs

@@ -6,19 +6,28 @@ use defmt::*;
 use embassy_executor::Spawner;
 use embassy_stm32::bind_interrupts;
 use embassy_stm32::peripherals;
+use embassy_stm32::peripherals::{PA2, PA3};
+use embassy_stm32::gpio::{Input, Output, Pull, Speed, Level};
+use embassy_stm32::Peripherals;
 use embassy_stm32::usart::{BufferedInterruptHandler, BufferedUart, Config};
+use embassy_stm32::timer::low_level::Timer as HardwareTimer;
+use embassy_stm32::interrupt::{self, typelevel::TIM2 as TIM2_IRQ, Priority};
+use embassy_stm32::peripherals::TIM2;
 use embedded_io_async::{Read, Write};
+use embassy_stm32::time::Hertz;
 use embassy_time::{Timer, Duration, Instant};
-use static_cell::StaticCell;
 use embassy_futures::yield_now;
-use {defmt_rtt as _, panic_probe as _};
 use embassy_futures::select::{select, Either};
 use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
 use embassy_sync::pipe::Pipe;
+use embassy_sync::signal::Signal;
+use static_cell::StaticCell;
+use {defmt_rtt as _, panic_probe as _};
 use async_uart::safety::{preflight_and_suggest_yield_period, RX_PIPE_CAP, TX_PIPE_CAP};
 
 static UART_TX: Pipe<CriticalSectionRawMutex, TX_PIPE_CAP> = Pipe::new();
 static UART_RX: Pipe<CriticalSectionRawMutex, RX_PIPE_CAP> = Pipe::new();
+static TIM2_TICK: Signal<CriticalSectionRawMutex, ()> = Signal::new();
 
 bind_interrupts!(
     struct Irqs {
@@ -81,12 +90,28 @@ async fn main(spawner: Spawner) {
     info!("starting uart task");
     spawner.spawn(uart_task(usart)).unwrap();
 
-    let mut counter: u32 = 0;
+    let mut transfer: u32 = 16;
     let mut rx_buf = [0u8; 64];
     let mut last_yield = Instant::now();
 
+    // Software UART bits init
+    let mut tx = Output::new(p.PA2, Level::Low, Speed::Low);
+    let _rx = Input::new(p.PA3, Pull::Up);
+
+    let tim = HardwareTimer::new(p.TIM2);
+
+    // Configure for 230_400 Hz
+    tim.set_frequency(Hertz(cfg.baudrate*transfer));
+    tim.enable_update_interrupt(true);
+    tim.start();
+
     loop {
-        counter = counter.wrapping_add(1);
+
+        TIM2_TICK.wait().await;
+        tx.set_high();
+        TIM2_TICK.wait().await;
+        tx.set_low();
+
         // Poll RX pipe for new data (non-blocking)
         if let Ok(n) = UART_RX.try_read(&mut rx_buf) {
             if n > 0 {
@@ -108,3 +133,24 @@ async fn main(spawner: Spawner) {
         // Timer::after(Duration::from_secs(5)).await;
     }
 }
+
+#[embassy_stm32::interrupt]
+fn TIM2() {
+    use embassy_stm32::timer::CoreInstance;
+
+    // Access TIM2 core registers directly.
+    let regs = unsafe {
+        embassy_stm32::pac::timer::TimCore::from_ptr(
+            <peripherals::TIM2 as CoreInstance>::regs(),
+        )
+    };
+
+    // Clear update flag to avoid retriggering.
+    let sr = regs.sr().read();
+    if sr.uif() {
+        regs.sr().modify(|r| r.set_uif(false));
+
+        // Signal the waiting task that a tick occurred.
+        TIM2_TICK.signal(());
+    }
+}

semestralka_1/src/lib.rs

@@ -1,3 +1,3 @@
 #![no_std]
 pub mod safety;
-pub mod software_uart;
+// pub mod software_uart;

semestralka_1/src/software_uart/mod.rs

@@ -1 +1,4 @@
 // src/software_uart/mod.rs
+
+pub mod suart;
+pub use suart::*;

semestralka_1/src/software_uart/suart.rs

@@ -1,2 +1,19 @@
 // src/software_uart/suart.rs
 
+use embassy_stm32::peripherals::{PA2, PA3};
+use embassy_stm32::gpio::{Input, Output, Pull, Speed, Level};
+use embassy_stm32::Peripherals;
+use embassy_time::Timer;
+
+pub async fn suart_test(mut tx_pin: PA2, rx_pin: PA3) {
+    let mut tx = Output::new(tx_pin.into(), Level::Low, Speed::Low);
+    let _rx = Input::new(rx_pin.into(), Pull::Up);
+
+    loop {
+        tx.set_high();
+        Timer::after_millis(500).await;
+
+        tx.set_low();
+        Timer::after_millis(500).await;
+    }
+}