semestralka joinig all worlds together
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Filipriec
@@ -1,157 +1,92 @@
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// src/bin/main.rs
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#![no_std]
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#![no_main]
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use defmt::*;
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use embassy_executor::Spawner;
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use embassy_stm32::bind_interrupts;
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use embassy_stm32::peripherals;
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use embassy_stm32::peripherals::{PA2, PA3};
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use embassy_stm32::gpio::{Input, Output, Pull, Speed, Level};
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use embassy_stm32::Peripherals;
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use embassy_stm32::usart::{BufferedInterruptHandler, BufferedUart, Config};
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use embassy_stm32::timer::low_level::Timer as HardwareTimer;
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use embassy_stm32::interrupt::{self, typelevel::TIM2 as TIM2_IRQ, Priority};
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use embassy_stm32::peripherals::TIM2;
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use embedded_io_async::{Read, Write};
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use embassy_stm32::time::Hertz;
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use embassy_time::{Timer, Duration, Instant};
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use embassy_futures::yield_now;
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use embassy_futures::select::{select, Either};
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use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
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use embassy_sync::pipe::Pipe;
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use embassy_sync::signal::Signal;
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use embassy_stm32::dma::Request;
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use embassy_stm32::gpio::{Input, Output, Level, Pull, Speed};
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use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
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use embassy_stm32::dma::{TransferOptions, WritableRingBuffer};
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use dma_gpio::software_uart::{
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dma_timer::{init_tim6_for_uart, init_tim7_for_uart},
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gpio_dma_uart_tx::encode_uart_frames,
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gpio_dma_uart_rx::rx_dma_task,
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debug::dump_tim6_regs,
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};
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use dma_gpio::config::{BAUD, TX_PIN_BIT, RX_OVERSAMPLE, TX_OVERSAMPLE};
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use dma_gpio::config::{TX_RING_BYTES, RX_RING_BYTES, PIPE_RX_SIZE};
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use static_cell::StaticCell;
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use embassy_futures::yield_now;
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use {defmt_rtt as _, panic_probe as _};
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use async_uart::safety::{preflight_and_suggest_yield_period, RX_PIPE_CAP, TX_PIPE_CAP};
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static UART_TX: Pipe<CriticalSectionRawMutex, TX_PIPE_CAP> = Pipe::new();
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static UART_RX: Pipe<CriticalSectionRawMutex, RX_PIPE_CAP> = Pipe::new();
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static TIM2_TICK: Signal<CriticalSectionRawMutex, ()> = Signal::new();
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pub const TIM6_UP_REQ: Request = 4;
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bind_interrupts!(
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struct Irqs {
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USART1 => BufferedInterruptHandler<peripherals::USART1>;
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}
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);
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#[embassy_executor::task]
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async fn uart_task(mut uart: BufferedUart<'static>) {
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let mut rx_byte = [0u8; 1];
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let mut tx_buf = [0u8; 64];
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loop {
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// Wait for either RX or TX events.
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let rx_fut = uart.read(&mut rx_byte);
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let tx_fut = async {
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// Until there's outgoing data in TX pipe
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let n = UART_TX.read(&mut tx_buf).await;
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n
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};
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match select(rx_fut, tx_fut).await {
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// Incoming data from UART hardware
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Either::First(res) => {
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if let Ok(_) = res {
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// Forward to RX pipe
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let _ = UART_RX.write(&rx_byte).await;
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let _ = UART_TX.try_write(&rx_byte);
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}
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}
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// Outgoing data waiting in TX pipe
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Either::Second(n) => {
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unwrap!(uart.write(&tx_buf[..n]).await);
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}
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}
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}
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}
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static PIPE_RX: Pipe<CriticalSectionRawMutex, PIPE_RX_SIZE> = Pipe::new();
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static TX_RING: StaticCell<[u32; TX_RING_BYTES]> = StaticCell::new();
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static RX_RING: StaticCell<[u8; RX_RING_BYTES]> = StaticCell::new();
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#[embassy_executor::main]
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async fn main(spawner: Spawner) {
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info!("tititititi");
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let p = embassy_stm32::init(Default::default());
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static TX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
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static RX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
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let tx_buf = TX_BUF.init([0; 256]);
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let rx_buf = RX_BUF.init([0; 256]);
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let mut cfg = Config::default();
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cfg.baudrate = 230_400;
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info!("Hehe");
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// Call preflight and get the computed yield period
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let yield_period = preflight_and_suggest_yield_period(cfg.baudrate);
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let usart = BufferedUart::new(
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p.USART1,
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p.PA10, // RX
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p.PA9, // TX
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tx_buf,
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rx_buf,
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Irqs,
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cfg,
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).unwrap();
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info!("starting uart task");
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spawner.spawn(uart_task(usart)).unwrap();
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let mut transfer: u32 = 16;
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let mut rx_buf = [0u8; 64];
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let mut last_yield = Instant::now();
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// Software UART bits init
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let mut tx = Output::new(p.PA2, Level::Low, Speed::Low);
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let _rx = Input::new(p.PA3, Pull::Up);
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let _tx = Output::new(p.PA2, Level::High, Speed::VeryHigh);
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let tim = HardwareTimer::new(p.TIM2);
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init_tim6_for_uart(p.TIM6, BAUD, TX_OVERSAMPLE);
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init_tim7_for_uart(p.TIM7, BAUD, RX_OVERSAMPLE);
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// Configure for 230_400 Hz
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tim.set_frequency(Hertz(cfg.baudrate*transfer));
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tim.enable_update_interrupt(true);
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tim.start();
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dump_tim6_regs();
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tx.set_high();
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loop {
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// Safe one-time init from StaticCell
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let rx_ring: &mut [u8; RX_RING_BYTES] = RX_RING.init([0; RX_RING_BYTES]);
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let tx_ring_mem: &mut [u32; TX_RING_BYTES] = TX_RING.init([0; TX_RING_BYTES]);
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TIM2_TICK.wait().await;
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tx.set_low();
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TIM2_TICK.wait().await;
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// Spawn tasks
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spawner.spawn(rx_dma_task(p.GPDMA1_CH1, &PIPE_RX, rx_ring).unwrap());
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Timer::after(Duration::from_millis(1000)).await;
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// Poll RX pipe for new data (non-blocking)
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if let Ok(n) = UART_RX.try_read(&mut rx_buf) {
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if n > 0 {
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if let Ok(s) = core::str::from_utf8(&rx_buf[..n]) {
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info!("RX got: {}", s);
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} else {
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info!("RX got (non‑utf8): {:?}", &rx_buf[..n]);
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}
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}
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}
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// Create and start the TX DMA ring in main.
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// let bsrr_ptr = embassy_stm32::pac::GPIOA.bsrr().as_ptr() as *mut u32;
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let odr_ptr = embassy_stm32::pac::GPIOA.odr().as_ptr() as *mut u32;
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let mut tx_opts = TransferOptions::default();
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tx_opts.half_transfer_ir = true;
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tx_opts.complete_transfer_ir = true;
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// Guaranteed to yield before ISR RX buffer can overflow
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if Instant::now().duration_since(last_yield) >= yield_period {
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yield_now().await;
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last_yield = Instant::now();
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// info!("Yield mf {}", counter);
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}
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// Timer::after(Duration::from_micros(1)).await;
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// Timer::after(Duration::from_secs(5)).await;
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}
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}
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#[embassy_stm32::interrupt]
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fn TIM2() {
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use embassy_stm32::timer::CoreInstance;
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// Access TIM2 core registers directly.
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let regs = unsafe {
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embassy_stm32::pac::timer::TimCore::from_ptr(
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<peripherals::TIM2 as CoreInstance>::regs(),
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// SAFETY: tx_ring_mem is exclusive
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let mut tx_ring = unsafe {
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WritableRingBuffer::new(
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p.GPDMA1_CH0,
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TIM6_UP_REQ,
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odr_ptr,
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tx_ring_mem,
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tx_opts,
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)
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};
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// Start DMA
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tx_ring.start();
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info!("TX DMA ring started");
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// Clear update flag to avoid retriggering.
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let sr = regs.sr().read();
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if sr.uif() {
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regs.sr().modify(|r| r.set_uif(false));
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let mut frame_buf = [0u32; 4096];
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// Signal the waiting task that a tick occurred.
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TIM2_TICK.signal(());
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loop {
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info!("tick start");
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// Timer::after(Duration::from_millis(100)).await;
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// info!("tick end");
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let used = encode_uart_frames(
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TX_PIN_BIT,
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b"Hello marshmallow\r\n",
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&mut frame_buf,
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)
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.await;
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if used == 0 {
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info!("encode_uart_frames() produced 0 words, skipping write");
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yield_now().await;
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continue;
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}
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let _ = tx_ring.write_exact(&frame_buf[..used]).await;
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info!("text");
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yield_now().await;
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}
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}
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