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testing, not owrking 1d yet

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Filipriec
2025-11-18 19:39:51 +01:00
parent 0a0ff0f38a
commit 45df1e87e4
2 changed files with 34 additions and 14 deletions
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44
semestralka_1d_rx_bez_dma/src/bin/main.rs
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@@ -27,6 +27,9 @@ use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
use dma_gpio::hw_uart_internal::usart2;
use dma_gpio::hw_uart_internal::driver::uart_task as uart_task_internal;
use dma_gpio::config::{PIPE_INT_TX, PIPE_INT_RX};
use dma_gpio::software_uart::uart_emulation::decode_uart_samples;
use dma_gpio::config::UART_CFG;
use embassy_stm32::pac::TIM6;
use embassy_time::{Duration, Timer};
use {defmt_rtt as _, panic_probe as _};
@@ -105,24 +108,41 @@ async fn main(spawner: Spawner) {
// EDN OF SOFTWARE UART
let tim6_regs = TIM6;
let mut levels = [0u8; 512];
let mut idx = 0usize;
let mut buf = [0u8; 32];
let mut last_state: u8 = 0;
loop {
info!("tick start");
// info!("tick start");
// RX pin should be READ in here and print via info!
//
let bit = rx_pin.is_high();
info!("Rx_pin read (high): {}", bit);
if bit as u8 != last_state {
info!(
"SW RX -> PD6 changed, new state = {}",
if bit { "HIGH" } else { "LOW" }
);
last_state = bit as u8;
continue;
while !tim6_regs.sr().read().uif() {
yield_now().await;
}
// Clear interrupt flag
tim6_regs.sr().modify(|w| w.set_uif(false));
// Sample PD6 level
let bit = rx_pin.is_high();
levels[idx] = bit as u8;
idx += 1;
// When buffer full, decode UART samples into bytes
if idx >= levels.len() {
let decoded = decode_uart_samples(&levels, RX_OVERSAMPLE, &UART_CFG);
if !decoded.is_empty() {
info!("SW RX decoded: {:a}", decoded.as_slice());
}
idx = 0;
}
let n1 = PIPE_INT_TX.read(&mut buf).await;
if n1 > 0 {
info!("PIPE_INT_TX received: {:a}", &buf[..n1]);
}
Timer::after(Duration::from_millis(1)).await;
yield_now().await;
}
@@ -138,7 +158,7 @@ pub async fn bridge_usart1_rx_to_usart2_tx(
let n = usart1_rx.read(&mut buf).await;
if n > 0 {
let _ = usart2_tx.write(&buf[..n]).await;
info!("bridge: USART1 -> USART2 sent {} bytes", n);
// info!("bridge: USART1 -> USART2 sent {} bytes", n);
}
yield_now().await;
}
@@ -154,7 +174,7 @@ pub async fn bridge_usart2_rx_to_usart1_tx(
let n = usart2_rx.read(&mut buf).await;
if n > 0 {
let _ = usart1_tx.write(&buf[..n]).await;
info!("bridge: USART2 -> USART1 sent {} bytes", n);
// info!("bridge: USART2 -> USART1 sent {} bytes", n);
}
yield_now().await;
}

2
semestralka_1d_rx_bez_dma/src/config.rs
View File

@@ -3,7 +3,7 @@ use crate::software_uart::uart_emulation::{Parity, StopBits, UartConfig};
use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
use embassy_sync::pipe::Pipe;
pub const BAUD: u32 = 115_200;
pub const BAUD: u32 = 9_600;
// pub const TX_PIN_BIT: u8 = 2; // PA2
// pub const RX_PIN_BIT: u8 = 3; // PA3
pub const TX_PIN_BIT: u8 = 0; // PB2