filipriec/stm32_rust
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FINAL FIX WORKING OH MY GOSH YES, We have to leak the timer to keep it toggled on after going out of scope to not call destructor

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Priec
2025-10-31 11:46:21 +01:00
parent 172dd899f9
commit 457d783d3b
1 changed files with 3 additions and 0 deletions
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3
dma_gpio/src/dma_timer.rs
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@@ -6,12 +6,14 @@ use embassy_stm32::{
timer::low_level::Timer, timer::low_level::Timer,
Peri, Peri,
}; };
use core::mem;
use embassy_stm32::pac::timer::vals::Urs; use embassy_stm32::pac::timer::vals::Urs;
/// Initializes TIM6 to tick at `baud * oversample` frequency. /// Initializes TIM6 to tick at `baud * oversample` frequency.
/// Each TIM6 update event triggers one DMA beat. /// Each TIM6 update event triggers one DMA beat.
pub fn init_tim6_for_uart<'d>(tim6: Peri<'d, TIM6>, baud: u32, oversample: u16) { pub fn init_tim6_for_uart<'d>(tim6: Peri<'d, TIM6>, baud: u32, oversample: u16) {
rcc::enable_and_reset::<TIM6>();
let ll = Timer::new(tim6); let ll = Timer::new(tim6);
let f_tim6 = rcc::frequency::<TIM6>().0; let f_tim6 = rcc::frequency::<TIM6>().0;
@@ -45,4 +47,5 @@ pub fn init_tim6_for_uart<'d>(tim6: Peri<'d, TIM6>, baud: u32, oversample: u16)
w.set_udis(false); w.set_udis(false);
w.set_urs(Urs::ANY_EVENT); w.set_urs(Urs::ANY_EVENT);
}); });
mem::forget(ll);
} }