complete movement, some parts are destroyed and not moved yet

dma_gpio/src/software_uart/debug.rs

@@ -0,0 +1,43 @@
+// src/software_uart/debug.rs
+use defmt::info;
+
+pub fn dump_tim6_regs() {
+    use embassy_stm32::pac::timer::TimBasic;
+    let tim = unsafe { TimBasic::from_ptr(0x4000_1000usize as _) };
+    let sr = tim.sr().read();
+    let dier = tim.dier().read();
+    let cr1 = tim.cr1().read();
+    let arr = tim.arr().read().arr();
+    let psc = tim.psc().read();
+    info!(
+        "TIM6: CR1.CEN={} DIER.UDE={} SR.UIF={} PSC={} ARR={}",
+        cr1.cen(),
+        dier.ude(),
+        sr.uif(),
+        psc,
+        arr
+    );
+}
+
+pub fn dump_dma_ch0_regs() {
+    use embassy_stm32::pac::gpdma::Gpdma;
+    let dma = unsafe { Gpdma::from_ptr(0x4002_0000usize as _) };
+    let ch = dma.ch(0);
+    let cr = ch.cr().read();
+    let tr1 = ch.tr1().read();
+    let tr2 = ch.tr2().read();
+    let br1 = ch.br1().read();
+    info!(
+        "GPDMA1_CH0: EN={} PRIO={} SDW={} DDW={} SINC={} DINC={} REQSEL={} SWREQ={} DREQ={} BNDT={}",
+        cr.en(),
+        cr.prio(),
+        tr1.sdw(),
+        tr1.ddw(),
+        tr1.sinc(),
+        tr1.dinc(),
+        tr2.reqsel(),
+        tr2.swreq(),
+        tr2.dreq(),
+        br1.bndt()
+    );
+}

dma_gpio/src/software_uart/dma_timer.rs

@@ -0,0 +1,58 @@
+// src/dma_timer.rs
+
+use embassy_stm32::{
+    peripherals::{TIM6, TIM7},
+    rcc,
+    timer::low_level::Timer,
+    Peri,
+};
+use core::mem;
+use embassy_stm32::timer::BasicInstance;
+use embassy_stm32::pac::timer::vals::Urs;
+
+/// Initializes TIM6 to tick at `baud * oversample` frequency.
+/// Each TIM6 update event triggers one DMA beat.
+pub fn init_tim6_for_uart<'d>(tim6: Peri<'d, TIM6>, baud: u32, oversample: u16) {
+    rcc::enable_and_reset::<TIM6>();
+    let ll = Timer::new(tim6);
+    configure_basic_timer(&ll, baud, oversample);
+    mem::forget(ll);
+}
+
+/// Initializes TIM7 to tick at `baud * oversample` frequency.
+/// Each TIM7 update event triggers one DMA beat.
+pub fn init_tim7_for_uart<'d>(tim7: Peri<'d, TIM7>, baud: u32, oversample: u16) {
+    rcc::enable_and_reset::<TIM7>();
+    let ll = Timer::new(tim7);
+    configure_basic_timer(&ll, baud, oversample);
+    mem::forget(ll);
+}
+
+// Shared internal helper — identical CR1/ARR setup
+fn configure_basic_timer<T: BasicInstance>(ll: &Timer<'_, T>, baud: u32, oversample: u16) {
+    let f_timer = rcc::frequency::<T>().0;
+    let target = baud.saturating_mul(oversample.max(1) as u32).max(1);
+
+    // Compute ARR (prescaler = 0)
+    let mut arr = (f_timer / target).saturating_sub(1) as u16;
+    if arr == 0 { arr = 1; }
+
+    ll.regs_basic().cr1().write(|w| {
+        w.set_cen(false);
+        w.set_opm(false);
+        w.set_udis(false);
+        w.set_urs(Urs::ANY_EVENT);
+    });
+
+    ll.regs_basic().psc().write_value(0u16);
+    ll.regs_basic().arr().write(|w| w.set_arr(arr));
+    ll.regs_basic().dier().modify(|w| w.set_ude(true));
+    ll.regs_basic().egr().write(|w| w.set_ug(true));
+
+    ll.regs_basic().cr1().write(|w| {
+        w.set_opm(false);
+        w.set_cen(true);
+        w.set_udis(false);
+        w.set_urs(Urs::ANY_EVENT);
+    });
+}

dma_gpio/src/software_uart/gpio_dma_uart_rx.rs

@@ -0,0 +1,57 @@
+// src/gpio_dma_uart_rx.rs
+use embassy_stm32::{
+    dma::{Request, Transfer, TransferOptions},
+    peripherals::GPDMA1_CH1,
+    Peri,
+};
+use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
+
+// RM0456 tabulka 137
+pub const TIM7_UP_REQ: Request = 5;
+
+pub struct GpioDmaRx<'d, const N: usize> {
+    ch: Peri<'d, GPDMA1_CH1>,
+    pin_bit: u8,
+    buf: &'d mut [u32; N],
+    opts: TransferOptions,
+    pipe_rx: &'d Pipe<CriticalSectionRawMutex, 256>,
+}
+
+impl<'d, const N: usize> GpioDmaRx<'d, N> {
+    pub fn new(
+        ch: Peri<'d, GPDMA1_CH1>,
+        pin_bit: u8,
+        buf: &'d mut [u32; N],
+        pipe_rx: &'d Pipe<CriticalSectionRawMutex, 256>,
+    ) -> Self {
+        Self {
+            ch,
+            pin_bit,
+            buf,
+            opts: TransferOptions::default(),
+            pipe_rx,
+        }
+    }
+
+    pub async fn run(&mut self) -> ! {
+        loop {
+            let gpioa_idr_addr = embassy_stm32::pac::GPIOA.as_ptr() as *mut u32;
+
+            unsafe {
+                Transfer::new_read(
+                    self.ch.reborrow(),
+                    TIM7_UP_REQ,
+                    gpioa_idr_addr,
+                    &mut self.buf[..],
+                    self.opts,
+                )
+            }
+            .await;
+
+            for &word in self.buf.iter() {
+                let bit_high = ((word >> self.pin_bit) & 1) as u8;
+                self.pipe_rx.write(&[bit_high]).await;
+            }
+        }
+    }
+}

dma_gpio/src/software_uart/gpio_dma_uart_tx.rs

@@ -0,0 +1,168 @@
+// src/gpio_dma_uart.rs
+use embassy_stm32::{
+    dma::{Request, Transfer, TransferOptions},
+    peripherals::GPDMA1_CH0,
+    Peri,
+};
+use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
+
+// kapitola 17.4.11 - 2 casovace pre 2 DMA
+pub const TIM6_UP_REQ: Request = 4; // Table 137: tim6_upd_dma, strana 687 STM32U5xx datasheet
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Parity {
+    None,
+    Even,
+    Odd,
+}
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum StopBits {
+    One,
+    Two,
+}
+
+#[derive(Clone, Copy, Debug)]
+pub struct UartConfig {
+    pub data_bits: u8, // 5..=8 bitov strana 16 TI_uart
+    pub parity: Parity,
+    pub stop_bits: StopBits,
+}
+
+impl Default for UartConfig {
+    fn default() -> Self {
+        Self {
+            data_bits: 8,
+            parity: Parity::None,
+            stop_bits: StopBits::One,
+        }
+    }
+}
+
+pub struct GpioDmaBsrrTx<'d> {
+    ch: Peri<'d, GPDMA1_CH0>,
+    bsrr: *mut u32,
+    opts: TransferOptions,
+}
+
+impl<'d> GpioDmaBsrrTx<'d> {
+    // Constructor. Hides the raw register pointer internally.
+    pub fn new(ch: Peri<'d, GPDMA1_CH0>) -> Self {
+        let bsrr = embassy_stm32::pac::GPIOA.bsrr().as_ptr() as *mut u32;
+        Self {
+            ch,
+            bsrr,
+            opts: TransferOptions::default(),
+        }
+    }
+
+    // Safe API: perform one timer-paced DMA write of a single 32-bit BSRR word.
+    pub async fn write_word(&mut self, word: u32) {
+        let buf = [word];
+        // Safety: bsrr is a valid 32-bit aligned register, buf lives until DMA completes,
+        // request selects TIM6_UP, which paces one beat per update.
+        unsafe {
+            Transfer::new_write(
+                self.ch.reborrow(),
+                TIM6_UP_REQ,
+                &buf,
+                self.bsrr,
+                self.opts,
+            )
+        }
+        .await;
+    }
+}
+
+// Build up to 12 BSRR words for one UART frame on a given GPIO bit.
+// Format: 1 START (low), N data (LSB first), optional PARITY, STOP(1/2 -> here 1 or 2 ticks).
+// BSRR je safe atomic write only shortcut
+pub fn encode_uart_byte_cfg(
+    pin_bit: u8,
+    data: u8,
+    cfg: &UartConfig,
+    out: &mut [u32; 12],
+) -> usize {
+    // Dokumentacia strana 636 13.4.7
+    // set bit - HIGH, reset bit - LOW (BSRR)
+    let set_high = |bit: u8| -> u32 { 1u32 << bit };
+    let set_low = |bit: u8| -> u32 { 1u32 << (bit as u32 + 16) };
+
+    let mut idx = 0usize;
+
+    // START bit (LOW)
+    out[idx] = set_low(pin_bit);
+    idx += 1;
+
+    // Data bits, LSB first (5..=8)
+    let nbits = cfg.data_bits.clamp(5, 8);
+    for i in 0..nbits {
+        let one = ((data >> i) & 1) != 0;
+        out[idx] = if one { set_high(pin_bit) } else { set_low(pin_bit) };
+        idx += 1;
+    }
+
+    // Optional parity
+    match cfg.parity {
+        Parity::None => {}
+        Parity::Even | Parity::Odd => {
+            // Count ones
+            let mask: u8 = if nbits == 8 { 0xFF } else { (1u16 << nbits) as u8 - 1 };
+            let ones = (data & mask).count_ones() & 1; // 0=even, 1=odd
+            let par_bit_is_one = match cfg.parity {
+                Parity::Even => ones == 1, // make total ones even
+                Parity::Odd => ones == 0,  // make total ones odd
+                _ => false,
+            };
+            out[idx] = if par_bit_is_one {
+                set_high(pin_bit)
+            } else {
+                set_low(pin_bit)
+            };
+            idx += 1;
+        }
+    }
+
+    // STOP bits (HIGH)
+    //  - STB=0 => 1 stop bit
+    //  - STB=1 => 2 stop bits
+    let stop_ticks = match cfg.stop_bits {
+        StopBits::One => 1usize,
+        StopBits::Two => 2usize,
+    };
+    for _ in 0..stop_ticks {
+        out[idx] = set_high(pin_bit);
+        idx += 1;
+    }
+
+    idx
+}
+
+// Push UART frames for a whole byte slice into a Pipe.
+pub async fn write_uart_frames_to_pipe<const N: usize>(
+    pipe: &Pipe<CriticalSectionRawMutex, N>,
+    pin_bit: u8,
+    bytes: &[u8],
+    cfg: &UartConfig,
+) {
+    for &b in bytes {
+        let mut frame = [0u32; 12];
+        let used = encode_uart_byte_cfg(pin_bit, b, cfg, &mut frame);
+        for w in &frame[..used] {
+            pipe.write(&w.to_le_bytes()).await;
+        }
+    }
+}
+
+// Optional: emit a BREAK (line LOW for 'bits' bit-times).
+pub async fn write_break_to_pipe<const N: usize>(
+    pipe: &Pipe<CriticalSectionRawMutex, N>,
+    pin_bit: u8,
+    bits: usize,
+) {
+    let set_low = |bit: u8| -> u32 { 1u32 << (bit as u32 + 16) };
+    let word = set_low(pin_bit);
+    for _ in 0..bits {
+        pipe.write(&word.to_le_bytes()).await;
+    }
+}

dma_gpio/src/software_uart/mod.rs

@@ -0,0 +1,13 @@
+// src/software_uart/mod.rs
+
+pub mod gpio_dma_uart_tx;
+pub mod gpio_dma_uart_rx;
+pub mod dma_timer;
+pub mod runtime;
+pub mod debug;
+
+pub use gpio_dma_uart_tx::*;
+pub use gpio_dma_uart_rx::*;
+pub use dma_timer::*;
+pub use runtime::*;
+pub use debug::*;

dma_gpio/src/software_uart/runtime.rs

@@ -0,0 +1,61 @@
+// src/software_uart/runtime.rs
+use defmt::{info, warn};
+use embassy_executor::task;
+use embassy_stm32::{
+    dma::{ReadableRingBuffer as DmaRingRx, TransferOptions},
+    peripherals::{GPDMA1_CH0, GPDMA1_CH1},
+    Peri,
+};
+use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
+use embassy_time::Duration;
+use crate::software_uart::{
+    gpio_dma_uart_rx::TIM7_UP_REQ, gpio_dma_uart_tx::GpioDmaBsrrTx,
+    debug::{dump_dma_ch0_regs, dump_tim6_regs},
+};
+
+/// RX DMA task: reads GPIO samples paced by TIM7 and fills PIPE_RX
+#[task]
+pub async fn rx_dma_task(ch: Peri<'static, GPDMA1_CH1>) {
+    let ring = unsafe { &mut RX_RING };
+    let gpioa_idr = embassy_stm32::pac::GPIOA.idr().as_ptr() as *mut u8;
+
+    let mut opts = TransferOptions::default();
+    opts.half_transfer_ir = true;
+    opts.complete_transfer_ir = true;
+
+    let mut rx = unsafe { DmaRingRx::new(ch, TIM7_UP_REQ, gpioa_idr, ring, opts) };
+    rx.start();
+
+    let mut chunk = [0u8; 256];
+    loop {
+        let _ = rx.read_exact(&mut chunk).await;
+        PIPE_RX.write(&chunk).await;
+    }
+}
+
+/// TX DMA task: dequeues prebuilt frames from PIPE_TX and writes to GPIOA.BSRR
+#[task]
+pub async fn tx_dma_task(ch: Peri<'static, GPDMA1_CH0>) {
+    let mut tx = GpioDmaBsrrTx::new(ch);
+    info!("DMA TX task started");
+
+    loop {
+        let mut b = [0u8; 4];
+        let n = PIPE_TX.read(&mut b).await;
+        if n != 4 {
+            continue;
+        }
+
+        let w = u32::from_le_bytes(b);
+        info!("DMA write 0x{:08X} -> GPIOA.BSRR", w);
+
+        match embassy_time::with_timeout(Duration::from_millis(20), tx.write_word(w)).await {
+            Ok(()) => {}
+            Err(_) => {
+                warn!("DMA timeout: no TIM6 request");
+                dump_tim6_regs();
+                dump_dma_ch0_regs();
+            }
+        }
+    }
+}