complete movement, some parts are destroyed and not moved yet
This commit is contained in:
@@ -1,178 +1,62 @@
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// src/bin/main.rs
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#![no_std]
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#![no_main]
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use defmt::*;
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use embassy_executor::Spawner;
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use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
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use embassy_stm32::gpio::{Input, Output, Level, Pull, Speed};
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use embassy_time::{Duration, Timer};
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use dma_gpio::dma_timer::init_tim6_for_uart;
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use dma_gpio::dma_timer::init_tim7_for_uart;
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use embassy_stm32::gpio::Input;
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use embassy_stm32::gpio::Pull;
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use dma_gpio::gpio_dma_uart_rx::TIM7_UP_REQ;
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use embassy_stm32::dma::{ReadableRingBuffer as DmaRingRx, TransferOptions};
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use dma_gpio::software_uart::{
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dma_timer::{init_tim6_for_uart, init_tim7_for_uart},
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gpio_dma_uart_tx::{write_uart_frames_to_pipe, UartConfig, Parity, StopBits},
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runtime::{rx_dma_task, tx_dma_task},
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debug::dump_tim6_regs,
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};
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use {defmt_rtt as _, panic_probe as _};
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use embassy_stm32::{
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gpio::{Level, Output, Speed},
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peripherals::GPDMA1_CH0,
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peripherals::GPDMA1_CH1,
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};
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use embassy_stm32::Peri;
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use dma_gpio::gpio_dma_uart_tx::{
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write_uart_frames_to_pipe, GpioDmaBsrrTx, Parity, StopBits, UartConfig,
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};
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static PIPE_TX: Pipe<CriticalSectionRawMutex, 256> = Pipe::new();
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static PIPE_RX: Pipe<CriticalSectionRawMutex, 256> = Pipe::new();
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// Baud rate: one TIM6 update equals one UART bit-time
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/// SOFTWARE UART CONFIGURATION
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const BAUD: u32 = 115_200;
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const TX_PIN_BIT: u8 = 2; // PA2
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const TX_OVERSAMPLE: u16 = 1;
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const RX_OVERSAMPLE: u16 = 16;
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const PIPE_TX_SIZE: usize = 256;
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const PIPE_RX_SIZE: usize = 256;
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const RX_RING_BYTES: usize = 4096;
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const UART_CFG: UartConfig = UartConfig {
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data_bits: 8,
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parity: Parity::None,
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stop_bits: StopBits::One,
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};
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static PIPE_TX: Pipe<CriticalSectionRawMutex, PIPE_TX_SIZE> = Pipe::new();
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static PIPE_RX: Pipe<CriticalSectionRawMutex, PIPE_RX_SIZE> = Pipe::new();
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// Large hardware RX DMA circular buffer, scales with oversampling rate
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static mut RX_RING: [u8; RX_RING_BYTES] = [0; RX_RING_BYTES];
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fn dump_tim6_regs() {
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// PAC path for STM32U5: module `tim6`, type `Tim6` with ptr()
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use embassy_stm32::pac::timer::TimBasic;
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let tim = unsafe { TimBasic::from_ptr(0x4000_1000usize as _) };
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let sr = tim.sr().read();
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let dier = tim.dier().read();
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let cr1 = tim.cr1().read();
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let arr = tim.arr().read().arr();
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let psc = tim.psc().read();
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info!(
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"TIM6: CR1.CEN={} DIER.UDE={} SR.UIF={} PSC={} ARR={}",
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cr1.cen(),
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dier.ude(),
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sr.uif(),
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psc,
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arr
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);
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}
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fn dump_dma_ch0_regs() {
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// PAC path for GPDMA1: module `gpdma1`, type `Gpdma1`
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use embassy_stm32::pac::gpdma::Gpdma;
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let dma = unsafe { Gpdma::from_ptr(0x4002_0000usize as _) };
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let ch = dma.ch(0);
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let cr = ch.cr().read();
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let tr1 = ch.tr1().read();
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let tr2 = ch.tr2().read();
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let br1 = ch.br1().read();
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info!(
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"GPDMA1_CH0: EN={} PRIO={} SDW={} DDW={} SINC={} DINC={} REQSEL={} SWREQ={} DREQ={} BNDT={}",
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cr.en(),
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cr.prio(),
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tr1.sdw(),
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tr1.ddw(),
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tr1.sinc(),
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tr1.dinc(),
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tr2.reqsel(),
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tr2.swreq(),
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tr2.dreq(),
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br1.bndt()
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);
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}
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#[embassy_executor::main]
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async fn main(spawner: Spawner) {
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let p = embassy_stm32::init(Default::default());
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info!("Hehe");
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// Initialize peripheral access
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let mut p = embassy_stm32::init(Default::default());
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info!("UART DMA demo starting...");
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// PA3 as Rx "wire"
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let pa3_rx = Input::new(p.PA3, Pull::Up);
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// GPIO setup
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let rx = Input::new(p.PA3, Pull::Up);
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let _tx = Output::new(p.PA2, Level::High, Speed::VeryHigh);
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// PA2 is the TX "wire"
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let _pa2 = Output::new(p.PA2, Level::High, Speed::VeryHigh);
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// drop(_pa2);
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init_tim6_for_uart(p.TIM6, BAUD, TX_OVERSAMPLE); // TX
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init_tim7_for_uart(p.TIM7, BAUD, RX_OVERSAMPLE); // RX
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dump_tim6_regs();
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// Timer setup
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init_tim6_for_uart(p.TIM6, BAUD, TX_OVERSAMPLE);
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init_tim7_for_uart(p.TIM7, BAUD, RX_OVERSAMPLE);
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dump_tim6_regs(); // debug
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// Start DMA consumer task
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spawner.spawn(tx_dma_task(p.GPDMA1_CH0).unwrap());
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spawner.spawn(rx_dma_task(p.GPDMA1_CH1).unwrap());
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// Spawn DMA tasks
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spawner.spawn(tx_dma_task(p.GPDMA1_CH0)).unwrap();
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spawner.spawn(rx_dma_task(p.GPDMA1_CH1)).unwrap();
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// Example: transmit a string as UART frames via the Pipe
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// UART config (8N1 default)
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let uart_cfg = UartConfig {
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data_bits: 8,
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parity: Parity::None,
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stop_bits: StopBits::One,
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};
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// Main loop: send data periodically
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loop {
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write_uart_frames_to_pipe(
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&PIPE_TX,
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TX_PIN_BIT,
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b"Hello marshmallow\r\n",
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&UART_CFG,
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).await;
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write_uart_frames_to_pipe(&PIPE_TX, TX_PIN_BIT, b"Hello marshmallow\r\n", &uart_cfg).await;
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Timer::after(Duration::from_secs(2)).await;
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}
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}
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#[embassy_executor::task]
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async fn rx_dma_task(ch: Peri<'static, GPDMA1_CH1>) {
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// SAFETY Own the static RX buffer exclusively.
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let ring_ptr = core::ptr::addr_of_mut!(RX_RING);
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let ring = unsafe { &mut *ring_ptr };
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// DMA will read samples from GPIOA input register.
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// Each sample is one byte (PA0..PA7). PA3 lives in bit 3.
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let gpioa_idr = embassy_stm32::pac::GPIOA.idr().as_ptr() as *mut u8;
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let mut opts = TransferOptions::default();
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opts.half_transfer_ir = true; // wake at half buffer
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opts.complete_transfer_ir = true; // wake at full buffer
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// Start hardware-linked circular DMA into ring.
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let mut rx = unsafe { DmaRingRx::new(ch, TIM7_UP_REQ, gpioa_idr, ring, opts) };
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rx.start();
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// Drain in fixed chunks when CPU has time
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let mut chunk = [0u8; 256];
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loop {
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// Wait for a full chunk
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// Wakes on half/full buffer events
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let _ = rx.read_exact(&mut chunk).await;
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// Forward raw samples to PIPE_RX (decode later)
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PIPE_RX.write(&chunk).await;
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}
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}
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#[embassy_executor::task]
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async fn tx_dma_task(ch: Peri<'static, GPDMA1_CH0>) {
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let mut tx = GpioDmaBsrrTx::new(ch);
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info!("DMA task started, waiting for frames...");
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loop {
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// Read one 32-bit BSRR word (4 bytes) from the Pipe
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let mut b = [0u8; 4];
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let n = PIPE_TX.read(&mut b).await;
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if n != 4 {
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continue;
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}
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let w = u32::from_le_bytes(b);
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info!("DMA write 0x{:08X} -> GPIOA.BSRR", w);
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match embassy_time::with_timeout(
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Duration::from_millis(20),
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tx.write_word(w),
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)
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.await
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{
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Ok(()) => {}
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Err(_) => {
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warn!("DMA timeout: no TIM6 request");
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dump_tim6_regs();
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dump_dma_ch0_regs();
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}
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}
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}
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}
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