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software uart is now a library

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Priec
2025-11-23 15:48:54 +01:00
parent 685067a75f
commit 4097ce1c7a
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2
semestralka_1_final_crate/software_uart/.cargo/config.toml Normal file
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[build]
target = "thumbv8m.main-none-eabihf"

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semestralka_1_final_crate/software_uart/Cargo.lock generated Normal file
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semestralka_1_final_crate/software_uart/Cargo.toml Normal file
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[package]
name = "software_uart"
version = "1.0.0"
edition = "2024"
license = "MIT OR Apache-2.0"
[dependencies]
cortex-m = { version = "0.7.7", features = ["inline-asm", "critical-section-single-core"] }
cortex-m-rt = "0.7.5"
panic-halt = "1.0.0"
embassy-executor = { path = "/home/priec/programs/embassy/embassy-executor", features = ["arch-cortex-m", "executor-thread"] }
embassy-futures = { path = "/home/priec/programs/embassy/embassy-futures" }
embassy-sync = { path = "/home/priec/programs/embassy/embassy-sync" }
embassy-time = { path = "/home/priec/programs/embassy/embassy-time", features = ["tick-hz-32_768"] }
embassy-hal-internal = { path = "/home/priec/programs/embassy/embassy-hal-internal" }
embassy-usb = { path = "/home/priec/programs/embassy/embassy-usb" }
embassy-stm32 = { path = "/home/priec/programs/embassy/embassy-stm32", features = ["unstable-pac", "stm32u575zi", "time-driver-tim2", "memory-x", "defmt"] }
embedded-hal = "1.0.0"
embedded-graphics = "0.8.1"
heapless = { version = "0.9.1", default-features = false }
micromath = "2.1.0"
tinybmp = "0.6.0"
panic-probe = { version = "1.0.0", features = ["defmt"] }
defmt-rtt = "1.1.0"
defmt = "1.0.1"
static_cell = "2.1.1"
embedded-io = "0.6.1"
embedded-io-async = "0.6.1"
[dev-dependencies]
defmt-test = "0.4.0"
[profile.dev]
opt-level = 3
codegen-units = 1

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semestralka_1_final_crate/software_uart/src/debug.rs Normal file
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// src/debug.rs
use defmt::info;
pub fn dump_tim6_regs() {
use embassy_stm32::pac::timer::TimBasic;
let tim = unsafe { TimBasic::from_ptr(0x4000_1000usize as _) };
let sr = tim.sr().read();
let dier = tim.dier().read();
let cr1 = tim.cr1().read();
let arr = tim.arr().read().arr();
let psc = tim.psc().read();
info!(
"TIM6: CR1.CEN={} DIER.UDE={} SR.UIF={} PSC={} ARR={}",
cr1.cen(),
dier.ude(),
sr.uif(),
psc,
arr
);
}
pub fn dump_dma_ch0_regs() {
use embassy_stm32::pac::gpdma::Gpdma;
let dma = unsafe { Gpdma::from_ptr(0x4002_0000usize as _) };
let ch = dma.ch(0);
let cr = ch.cr().read();
let tr1 = ch.tr1().read();
let tr2 = ch.tr2().read();
let br1 = ch.br1().read();
info!(
"GPDMA1_CH0: EN={} PRIO={} SDW={} DDW={} SINC={} DINC={} REQSEL={} SWREQ={} DREQ={} BNDT={}",
cr.en(),
cr.prio(),
tr1.sdw(),
tr1.ddw(),
tr1.sinc(),
tr1.dinc(),
tr2.reqsel(),
tr2.swreq(),
tr2.dreq(),
br1.bndt()
);
}

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semestralka_1_final_crate/software_uart/src/dma_timer.rs Normal file
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// src/dma_timer.rs
use embassy_stm32::{
peripherals::{TIM6, TIM7},
rcc,
timer::low_level::Timer,
Peri,
};
use core::mem;
use embassy_stm32::timer::BasicInstance;
use embassy_stm32::pac::timer::vals::Urs;
/// Initializes TIM6 to tick at `baud * oversample` frequency.
/// Each TIM6 update event triggers one DMA beat.
pub fn init_tim6_for_uart<'d>(tim6: Peri<'d, TIM6>, baud: u32, oversample: u16) {
rcc::enable_and_reset::<TIM6>();
let ll = Timer::new(tim6);
configure_basic_timer(&ll, baud, oversample);
mem::forget(ll);
}
/// Initializes TIM7 to tick at `baud * oversample` frequency.
/// Each TIM7 update event triggers one DMA beat.
pub fn init_tim7_for_uart<'d>(tim7: Peri<'d, TIM7>, baud: u32, oversample: u16) {
rcc::enable_and_reset::<TIM7>();
let ll = Timer::new(tim7);
configure_basic_timer(&ll, baud, oversample);
// Enable Update Interrupt (UIE)
ll.regs_basic().dier().modify(|w| {
w.set_ude(true);
w.set_uie(false);
});
mem::forget(ll);
}
// Shared internal helper — identical CR1/ARR setup
fn configure_basic_timer<T: BasicInstance>(ll: &Timer<'_, T>, baud: u32, oversample: u16) {
let f_timer = rcc::frequency::<T>().0;
let target = baud.saturating_mul(oversample.max(1) as u32).max(1);
// Compute ARR (prescaler = 0)
// let mut arr = (f_timer / target).saturating_sub(1) as u16;
let mut arr = ((f_timer + target / 2) / target).saturating_sub(1) as u16;
if arr == 0 { arr = 1; }
ll.regs_basic().cr1().write(|w| {
w.set_cen(false);
w.set_opm(false);
w.set_udis(false);
w.set_urs(Urs::ANY_EVENT);
});
ll.regs_basic().psc().write_value(0u16);
ll.regs_basic().arr().write(|w| w.set_arr(arr));
ll.regs_basic().dier().modify(|w| w.set_ude(true));
ll.regs_basic().egr().write(|w| w.set_ug(true));
// Clear spurious UIF from UG trigger
ll.regs_basic().sr().modify(|w| w.set_uif(false));
ll.regs_basic().cr1().write(|w| {
w.set_opm(false);
w.set_cen(true);
w.set_udis(false);
w.set_urs(Urs::ANY_EVENT);
});
}

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semestralka_1_final_crate/software_uart/src/gpio_dma_uart_rx.rs Normal file
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// src/runtime.rs
use embassy_executor::task;
use embassy_stm32::{
dma::Request,
peripherals::GPDMA1_CH1,
Peri,
};
use crate::config::RX_PIN_BIT;
use embassy_stm32::dma::{
ReadableRingBuffer,
TransferOptions,
};
use crate::config::{RX_OVERSAMPLE, UART_CFG};
use crate::decode_uart_samples;
use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
use embassy_futures::yield_now;
use defmt::info;
// datasheet tabulka 137
pub const TIM7_UP_REQ: Request = 5;
/// RX DMA task: reads GPIO samples paced by TIM7 and fills PIPE_RX
#[task]
pub async fn rx_dma_task(
ch: Peri<'static, GPDMA1_CH1>,
register: *mut u8,
ring: &'static mut [u8],
pipe_rx: &'static Pipe<CriticalSectionRawMutex, 4096>,
) {
let mut opts = TransferOptions::default();
opts.half_transfer_ir = true;
opts.complete_transfer_ir = true;
// SAFETY: ring is exclusive to this task
let mut rx = unsafe { ReadableRingBuffer::new(ch, TIM7_UP_REQ, register, ring, opts) };
rx.start();
// We read into the second half of a buffer, keeping "leftovers" in the first half.
const CHUNK_SIZE: usize = 4096;
const HISTORY_SIZE: usize = 512;
const TOTAL_BUF_SIZE: usize = HISTORY_SIZE + CHUNK_SIZE;
// Logic level buffer
let mut level_buf = [0u8; TOTAL_BUF_SIZE];
let mut valid_len = 0usize;
let mut raw_chunk = [0u8; CHUNK_SIZE];
loop {
let _ = rx.read_exact(&mut raw_chunk).await;
for (i, b) in raw_chunk.iter().enumerate() {
level_buf[valid_len + i] = ((*b >> RX_PIN_BIT) & 1) as u8;
}
let current_end = valid_len + CHUNK_SIZE;
let (decoded, consumed) = decode_uart_samples(
&level_buf[..current_end],
RX_OVERSAMPLE,
&UART_CFG
);
if !decoded.is_empty() {
pipe_rx.write(decoded.as_slice()).await;
for byte in decoded.as_slice() {
// info!("DMA BUFFER CHAR: {} (ASCII: {})", *byte, *byte as char);
}
}
// Shift remaining data to front
// We processed 'consumed' samples.
// We keep everything from 'consumed' up to 'current_end'.
let remaining = current_end - consumed;
// SAFETY if remaining > HISTORY_SIZE, we are in trouble (buffer too small / decoder stuck).
if remaining > 0 {
level_buf.copy_within(consumed..current_end, 0);
}
valid_len = remaining;
// If valid_len grows too large (decoder not consuming), we must discard to avoid panic on next write
if valid_len >= HISTORY_SIZE {
// Discard oldest to make space
// logic: we move the last (HISTORY_SIZE/2) to 0.
// This effectively "skips" garbage data.
let keep = HISTORY_SIZE / 2;
level_buf.copy_within(valid_len - keep..valid_len, 0);
valid_len = keep;
}
yield_now().await;
}
}

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semestralka_1_final_crate/software_uart/src/gpio_dma_uart_tx.rs Normal file
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// src/gpio_dma_uart_tx.rs
use embassy_executor::task;
use embassy_stm32::{
dma::{Request, Transfer, TransferOptions},
peripherals::GPDMA1_CH0,
Peri,
};
use embassy_futures::yield_now;
use defmt::info;
use crate::UartConfig;
use embassy_sync::pipe::Pipe;
use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
use crate::uart_emulation::encode_uart_byte_cfg;
pub const TIM6_UP_REQ: Request = 4;
pub async fn encode_uart_frames<'a>(
pin_bit: u8,
bytes: &[u8],
out_buf: &'a mut [u32],
uart_cfg: &UartConfig,
) -> usize {
let mut offset = 0;
for &b in bytes {
let mut frame = [0u32; 12];
let used = encode_uart_byte_cfg(pin_bit, b, uart_cfg, &mut frame);
if offset + used <= out_buf.len() {
out_buf[offset..offset + used].copy_from_slice(&frame[..used]);
offset += used;
} else {
break;
}
yield_now().await;
}
offset
}
#[task]
pub async fn tx_dma_task(
mut ch: Peri<'static, GPDMA1_CH0>,
register: *mut u32, // GPIOx_BSRR
_tx_ring_mem: &'static mut [u32],
pipe_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
tx_pin_bit: u8,
uart_cfg: &'static UartConfig,
) {
info!("TX DMA task ready (One‑shot)");
let mut frame_buf = [0u32; 4096];
let mut rx_buf = [0u8; 256];
let tim6 = embassy_stm32::pac::TIM6;
loop {
let n = pipe_rx.read(&mut rx_buf).await;
if n == 0 {
yield_now().await;
continue;
}
let used = encode_uart_frames(tx_pin_bit, &rx_buf[..n], &mut frame_buf, uart_cfg).await;
if used > 0 {
// Clear pending UIF
tim6.sr().write(|w| w.set_uif(false));
// Wait for the next UIF (next bit tick)
while !tim6.sr().read().uif() {
yield_now().await;
}
// Clear UIF so first DMA beat happens on the FOLLOWING tick
tim6.sr().write(|w| w.set_uif(false));
let mut tx_opts = TransferOptions::default();
tx_opts.half_transfer_ir = false;
tx_opts.complete_transfer_ir = true;
unsafe {
let transfer = Transfer::new_write(
ch.reborrow(),
TIM6_UP_REQ,
&frame_buf[..used],
register,
tx_opts,
);
transfer.await;
}
}
// info!("tx_dma_task sent {} words", used);
yield_now().await;
}
}

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semestralka_1_final_crate/software_uart/src/lib.rs Normal file
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// src/lib.rs
#![no_std]
pub mod gpio_dma_uart_tx;
pub mod gpio_dma_uart_rx;
pub mod dma_timer;
pub mod uart_emulation;
pub mod debug;
pub use gpio_dma_uart_tx::*;
pub use gpio_dma_uart_rx::*;
pub use dma_timer::*;
pub use uart_emulation::*;
pub use debug::*;

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semestralka_1_final_crate/software_uart/src/uart_emulation.rs Normal file
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// src/uart_emulation.rs
use heapless::Vec;
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Parity {
None,
Even,
Odd,
}
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum StopBits {
One,
Two,
}
#[derive(Clone, Copy, Debug)]
pub struct UartConfig {
pub data_bits: u8,
pub parity: Parity,
pub stop_bits: StopBits,
}
impl Default for UartConfig {
fn default() -> Self {
Self {
data_bits: 8,
parity: Parity::None,
stop_bits: StopBits::One,
}
}
}
/// Encodes one byte into a sequence of GPIO BSRR words
pub fn encode_uart_byte_cfg(
pin_bit: u8,
data: u8,
cfg: &UartConfig,
out: &mut [u32; 12],
) -> usize {
// GPIOx_BSRR register str. 636 kap. 13.4.7
let set_high = |bit: u8| -> u32 { 1u32 << bit };
// let set_low = |bit: u8| -> u32 { 0 }; // ODR
let set_low = |bit: u8| -> u32 { 1u32 << (bit as u32 + 16) }; // BSRR
let mut idx = 0usize;
// START bit (LOW)
out[idx] = set_low(pin_bit);
idx += 1;
// Data bits, LSB-first
let nbits = cfg.data_bits.clamp(5, 8);
for i in 0..nbits {
let one = ((data >> i) & 1) != 0;
out[idx] = if one { set_high(pin_bit) } else { set_low(pin_bit) };
idx += 1;
}
// Parity
match cfg.parity {
Parity::None => {}
Parity::Even | Parity::Odd => {
let mask: u8 = if nbits == 8 { 0xFF } else { (1u16 << nbits) as u8 - 1 };
let ones = (data & mask).count_ones() & 1;
let par_bit_is_one = match cfg.parity {
Parity::Even => ones == 1,
Parity::Odd => ones == 0,
_ => false,
};
out[idx] = if par_bit_is_one {
set_high(pin_bit)
} else {
set_low(pin_bit)
};
idx += 1;
}
}
// STOP bits (HIGH)
let stop_ticks = match cfg.stop_bits {
StopBits::One => 1usize,
StopBits::Two => 2usize,
};
for _ in 0..stop_ticks {
out[idx] = set_high(pin_bit);
idx += 1;
}
idx
}
/// Decode an oversampled stream of logic levels into UART bytes.
/// Returns (decoded bytes, number of samples consumed/processed).
pub fn decode_uart_samples(
samples: &[u8],
oversample: u16,
cfg: &UartConfig,
) -> (heapless::Vec<u8, 256>, usize) {
let mut out = Vec::<u8, 256>::new();
let mut idx = 0usize;
let nbits = cfg.data_bits as usize;
let ovs = oversample as usize;
// Calculate total frame width in samples to ensure we have enough data
// 1 start + n data + parity? + stops
let parity_bits = match cfg.parity {
Parity::None => 0,
_ => 1,
};
let stop_bits_count = match cfg.stop_bits {
StopBits::One => 1,
StopBits::Two => 2,
};
let frame_bits = 1 + nbits + parity_bits + stop_bits_count;
let frame_len = frame_bits * ovs;
// Majority vote over 3 samples centered at `i`
let get_bit = |i: usize| -> u8 {
let mut votes = 0;
// Check i-1, i, i+1. Saturating sub/add handles boundaries roughly.
if i > 0 && samples.get(i - 1).map_or(true, |&x| x != 0) {
votes += 1;
}
if samples.get(i).map_or(true, |&x| x != 0) {
votes += 1;
}
if samples.get(i + 1).map_or(true, |&x| x != 0) {
votes += 1;
}
if votes >= 2 {
1
} else {
0
}
};
// Loop while we have enough remaining samples for a full frame
while idx + frame_len <= samples.len() {
// Wait for falling edge (High -> Low)
// samples[idx] == 1 (Idle/Stop) && samples[idx+1] == 0 (Start)
if samples[idx] != 0 && samples[idx + 1] == 0 {
// Align to center of START bit
// Start bit begins at idx+1. Center is at idx + 1 + (ovs/2)
let center_offset = 1 + (ovs / 2);
let mut scan_idx = idx + center_offset;
// Validate Start Bit
if get_bit(scan_idx) != 0 {
idx += 1; // False start (noise), move on
continue;
}
// Move to center of first data bit
scan_idx += ovs;
// Read Data Bits
let mut data: u8 = 0;
for bit in 0..nbits {
if get_bit(scan_idx) == 1 {
data |= 1 << bit;
}
scan_idx += ovs;
}
// Skip Parity
if cfg.parity != Parity::None {
scan_idx += ovs;
}
// Validate Stop Bit (Must be 1)
// If stop bit is 0, it's a framing error. We reject the whole byte.
if get_bit(scan_idx) == 0 {
idx += 1; // Next sample
continue;
}
// Byte is valid
let _ = out.push(data);
// Active Resync: Fast-forward through the stop bit(s) and idle time
// scan_idx is currently at the center of the Stop bit.
idx = scan_idx;
// Advance while we are reading High (1).
// As soon as we see Low (0), we stop. That 0 is the beginning of the NEXT start bit.
// The outer loop expects `idx` to be the High *before* the start bit, so we will handle that.
while idx < samples.len() && samples[idx] != 0 {
idx += 1;
}
// Back up one step.
// The outer loop logic is: `if samples[idx] != 0 && samples[idx+1] == 0`.
// If we stopped at `idx` because it was 0, then `idx-1` was the last 1 (Idle).
if idx > 0 {
idx -= 1;
}
} else {
// No start bit detected here, move to next sample
idx += 1;
}
}
(out, idx)
}

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semestralka_1_final_lib/.cargo/config.toml Normal file
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[build]
target = "thumbv8m.main-none-eabihf"
[target.thumbv8m.main-none-eabihf]
runner = "probe-rs run --chip STM32U575ZITxQ"
rustflags = [
"-C", "linker=rust-lld",
"-C", "link-arg=-Tlink.x",
"-C", "link-arg=-Tdefmt.x",
"-C", "link-arg=--nmagic",
]
[package.metadata.cargo-flash]
chip = "STM32U575ZIT"

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/target

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semestralka_1_final_lib/Cargo.lock generated Normal file
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semestralka_1_final_lib/Cargo.toml Normal file
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[package]
authors = ["Priec <filippriec@gmail.com>"]
name = "dma_gpio"
edition = "2024"
version = "0.1.0"
[dependencies]
cortex-m = { version = "0.7.7", features = ["inline-asm", "critical-section-single-core"] }
cortex-m-rt = "0.7.5"
panic-halt = "1.0.0"
embassy-executor = { path = "/home/priec/programs/embassy/embassy-executor", features = ["arch-cortex-m", "executor-thread"] }
embassy-futures = { path = "/home/priec/programs/embassy/embassy-futures" }
embassy-sync = { path = "/home/priec/programs/embassy/embassy-sync" }
embassy-time = { path = "/home/priec/programs/embassy/embassy-time", features = ["tick-hz-32_768"] }
embassy-hal-internal = { path = "/home/priec/programs/embassy/embassy-hal-internal" }
embassy-usb = { path = "/home/priec/programs/embassy/embassy-usb" }
embassy-stm32 = { path = "/home/priec/programs/embassy/embassy-stm32", features = ["unstable-pac", "stm32u575zi", "time-driver-tim2", "memory-x", "defmt"] }
embedded-hal = "1.0.0"
embedded-graphics = "0.8.1"
heapless = { version = "0.9.1", default-features = false }
micromath = "2.1.0"
tinybmp = "0.6.0"
panic-probe = { version = "1.0.0", features = ["defmt"] }
defmt-rtt = "1.1.0"
defmt = "1.0.1"
static_cell = "2.1.1"
embedded-io = "0.6.1"
embedded-io-async = "0.6.1"
software_uart = { path = "../semestralka_1_final_crate/software_uart" }
[dev-dependencies]
defmt-test = "0.4.0"
[[test]]
name = "uart_emulation"
harness = false
[lib]
test = false
[[bin]]
name = "main"
path = "src/bin/main.rs"
test = false
[profile.dev]
opt-level = 3
codegen-units = 1

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semestralka_1_final_lib/LICENSE-APACHE Normal file
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Apache License
Version 2.0, January 2004
http://www.apache.org/licenses/
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APPENDIX: How to apply the Apache License to your work.
To apply the Apache License to your work, attach the following
boilerplate notice, with the fields enclosed by brackets "[]"
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23
semestralka_1_final_lib/LICENSE-MIT Normal file
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@@ -0,0 +1,23 @@
Permission is hereby granted, free of charge, to any
person obtaining a copy of this software and associated
documentation files (the "Software"), to deal in the
Software without restriction, including without
limitation the rights to use, copy, modify, merge,
publish, distribute, sublicense, and/or sell copies of
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is furnished to do so, subject to the following
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The above copyright notice and this permission notice
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of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF
ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.

23
semestralka_1_final_lib/Makefile Normal file
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TARGET = thumbv8m.main-none-eabihf
CHIP = STM32U575ZI
BIN = stm32u5-blinky
MODE ?= release
TARGET_DIR = target/$(TARGET)/$(MODE)
ELF = $(TARGET_DIR)/$(BIN)
PROBE = probe-rs
.PHONY: all build flash clean empty
all: build
build:
cargo build --$(MODE)
flash: build
$(PROBE) run --chip $(CHIP) $(ELF)
empty:
$(PROBE) erase --chip $(CHIP)
clean:
cargo clean

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semestralka_1_final_lib/README.md Normal file
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# `app-template`
> Quickly set up a [`probe-rs`] + [`defmt`] + [`flip-link`] embedded project
[`probe-rs`]: https://crates.io/crates/probe-rs
[`defmt`]: https://github.com/knurling-rs/defmt
[`flip-link`]: https://github.com/knurling-rs/flip-link
## Dependencies
### 1. `flip-link`:
```bash
cargo install flip-link
```
### 2. `probe-rs`:
Install probe-rs by following the instructions at <https://probe.rs/docs/getting-started/installation/>.
### 3. [`cargo-generate`]:
```bash
cargo install cargo-generate
```
[`cargo-generate`]: https://crates.io/crates/cargo-generate
> *Note:* You can also just clone this repository instead of using `cargo-generate`, but this involves additional manual adjustments.
## Setup
### 1. Initialize the project template
```bash
cargo generate \
--git https://github.com/knurling-rs/app-template \
--branch main \
--name my-app
```
If you look into your new `my-app` folder, you'll find that there are a few `TODO`s in the files marking the properties you need to set.
Let's walk through them together now.
### 2. Set `probe-rs` chip
Pick a chip from ` probe-rs chip list` and enter it into `.cargo/config.toml`.
If, for example, you have a nRF52840 Development Kit as used in one of [our exercises], replace `{{chip}}` with `nRF52840_xxAA`.
[our workshops]: https://rust-exercises.ferrous-systems.com
```diff
# .cargo/config.toml
-runner = ["probe-rs", "run", "--chip", "$CHIP", "--log-format=oneline"]
+runner = ["probe-rs", "run", "--chip", "nRF52840_xxAA", "--log-format=oneline"]
```
### 3. Adjust the compilation target
In `.cargo/config.toml`, pick the right compilation target for your board.
```diff
# .cargo/config.toml
[build]
-target = "thumbv6m-none-eabi" # Cortex-M0 and Cortex-M0+
-# target = "thumbv7m-none-eabi" # Cortex-M3
-# target = "thumbv7em-none-eabi" # Cortex-M4 and Cortex-M7 (no FPU)
-# target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
+target = "thumbv7em-none-eabihf" # Cortex-M4F (with FPU)
```
Add the target with `rustup`.
```bash
rustup target add thumbv7em-none-eabihf
```
### 4. Add a HAL as a dependency
In `Cargo.toml`, list the Hardware Abstraction Layer (HAL) for your board as a dependency.
For the nRF52840 you'll want to use the [`nrf52840-hal`].
[`nrf52840-hal`]: https://crates.io/crates/nrf52840-hal
```diff
# Cargo.toml
[dependencies]
-# some-hal = "1.2.3"
+nrf52840-hal = "0.14.0"
```
⚠️ Note for RP2040 users ⚠️
You will need to not just specify the `rp-hal` HAL, but a BSP (board support crate) which includes a second stage bootloader. Please find a list of available BSPs [here](https://github.com/rp-rs/rp-hal-boards#packages).
### 5. Import your HAL
Now that you have selected a HAL, fix the HAL import in `src/lib.rs`
```diff
// my-app/src/lib.rs
-// use some_hal as _; // memory layout
+use nrf52840_hal as _; // memory layout
```
### (6. Get a linker script)
Some HAL crates require that you manually copy over a file called `memory.x` from the HAL to the root of your project. For nrf52840-hal, this is done automatically so no action is needed. For other HAL crates, see their documentation on where to find an example file.
The `memory.x` file should look something like:
```text
MEMORY
{
FLASH : ORIGIN = 0x00000000, LENGTH = 1024K
RAM : ORIGIN = 0x20000000, LENGTH = 256K
}
```
The `memory.x` file is included in the `cortex-m-rt` linker script `link.x`, and so `link.x` is the one you should tell `rustc` to use (see the `.cargo/config.toml` file where we do that).
### 7. Run!
You are now all set to `cargo-run` your first `defmt`-powered application!
There are some examples in the `src/bin` directory.
Start by `cargo run`-ning `my-app/src/bin/hello.rs`:
```console
$ # `rb` is an alias for `run --bin`
$ cargo rb hello
Finished `dev` profile [optimized + debuginfo] target(s) in 0.01s
Running `probe-rs run --chip nrf52840_xxaa --log-format=oneline target/thumbv6m-none-eabi/debug/hello`
Erasing ✔ 100% [####################] 8.00 KiB @ 15.79 KiB/s (took 1s)
Programming ✔ 100% [####################] 8.00 KiB @ 13.19 KiB/s (took 1s) Finished in 1.11s
Hello, world!
$ echo $?
0
```
If you're running out of memory (`flip-link` bails with an overflow error), you can decrease the size of the device memory buffer by setting the `DEFMT_RTT_BUFFER_SIZE` environment variable. The default value is 1024 bytes, and powers of two should be used for optimal performance:
```console
$ DEFMT_RTT_BUFFER_SIZE=64 cargo rb hello
```
### (8. Set `rust-analyzer.linkedProjects`)
If you are using [rust-analyzer] with VS Code for IDE-like features you can add following configuration to your `.vscode/settings.json` to make it work transparently across workspaces. Find the details of this option in the [RA docs].
```json
{
"rust-analyzer.linkedProjects": [
"Cargo.toml",
"firmware/Cargo.toml",
]
}
```
[RA docs]: https://rust-analyzer.github.io/manual.html#configuration
[rust-analyzer]: https://rust-analyzer.github.io/
## Running tests
The template comes configured for running unit tests and integration tests on the target.
Unit tests reside in the library crate and can test private API; the initial set of unit tests are in `src/lib.rs`.
`cargo test --lib` will run those unit tests.
```console
$ cargo test --lib
Compiling example v0.1.0 (./knurling-rs/example)
Finished `test` profile [optimized + debuginfo] target(s) in 0.15s
Running unittests src/lib.rs (target/thumbv6m-none-eabi/debug/deps/example-2b0d0e25d141bf57)
Erasing ✔ 100% [####################] 8.00 KiB @ 15.99 KiB/s (took 1s)
Programming ✔ 100% [####################] 8.00 KiB @ 13.33 KiB/s (took 1s) Finished in 1.10s
(1/1) running `it_works`...
all tests passed!
```
Integration tests reside in the `tests` directory; the initial set of integration tests are in `tests/integration.rs`.
`cargo test --test integration` will run those integration tests.
Note that the argument of the `--test` flag must match the name of the test file in the `tests` directory.
```console
$ cargo test --test integration
Compiling example v0.1.0 (./knurling-rs/example)
Finished `test` profile [optimized + debuginfo] target(s) in 0.10s
Running tests/integration.rs (target/thumbv6m-none-eabi/debug/deps/integration-aaaff41151f6a722)
Erasing ✔ 100% [####################] 8.00 KiB @ 16.03 KiB/s (took 0s)
Programming ✔ 100% [####################] 8.00 KiB @ 13.19 KiB/s (took 1s) Finished in 1.11s
(1/1) running `it_works`...
all tests passed!
```
Note that to add a new test file to the `tests` directory you also need to add a new `[[test]]` section to `Cargo.toml`.
To run all the tests via `cargo test` the tests need to be explicitly disabled for all the existing binary targets.
See `Cargo.toml` for details on how to do this.
## Support
`app-template` is part of the [Knurling] project, [Ferrous Systems]' effort at
improving tooling used to develop for embedded systems.
If you think that our work is useful, consider sponsoring it via [GitHub
Sponsors].
## License
Licensed under either of
- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
http://www.apache.org/licenses/LICENSE-2.0)
- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
at your option.
### Contribution
Unless you explicitly state otherwise, any contribution intentionally submitted
for inclusion in the work by you, as defined in the Apache-2.0 license, shall be
licensed as above, without any additional terms or conditions.
[Knurling]: https://knurling.ferrous-systems.com
[Ferrous Systems]: https://ferrous-systems.com/
[GitHub Sponsors]: https://github.com/sponsors/knurling-rs

190
semestralka_1_final_lib/src/bin/main.rs Normal file
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// src/bin/main.rs
#![no_std]
#![no_main]
use defmt::*;
use core::cell::RefCell;
use cortex_m::interrupt::Mutex;
use embassy_executor::Spawner;
use embassy_futures::yield_now;
use embassy_sync::{
blocking_mutex::raw::CriticalSectionRawMutex,
channel::Channel,
pipe::Pipe,
};
use embassy_time::{Duration, Instant, Timer};
use embassy_stm32::{
bind_interrupts,
dma::Request,
gpio::{Input, Level, Output, Pull, Speed},
interrupt,
pac,
peripherals,
rcc::{self, Pll, PllDiv, PllMul, PllPreDiv, PllSource, Sysclk},
usart::{BufferedInterruptHandler, BufferedUart, Config},
Config as CPUConfig,
};
use static_cell::StaticCell;
use dma_gpio::config::{
BAUD, PIPE_HW_RX, PIPE_HW_TX, PIPE_INT_RX, PIPE_INT_TX, PIPE_SW_RX,
PIPE_SW_TX, RX_OVERSAMPLE, RX_RING_BYTES, TX_OVERSAMPLE, TX_RING_BYTES,
UART_CFG,
};
use dma_gpio::hw_uart_pc::{driver::uart_task, usart1};
use dma_gpio::hw_uart_internal::{
driver::uart_task as uart_task_internal,
usart2,
};
use dma_gpio::software_uart::{
debug::dump_tim6_regs,
decode_uart_samples,
dma_timer::{init_tim6_for_uart, init_tim7_for_uart},
gpio_dma_uart_rx::rx_dma_task,
gpio_dma_uart_tx::tx_dma_task,
};
use {defmt_rtt as _, panic_probe as _};
static PD6_BITS: Channel<CriticalSectionRawMutex, u8, 16384> = Channel::new();
bind_interrupts!(struct Irqs {
USART1 => BufferedInterruptHandler<peripherals::USART1>;
});
bind_interrupts!(struct Irqs2 {
USART2 => BufferedInterruptHandler<peripherals::USART2>;
});
// Software uart
pub const TIM6_UP_REQ: Request = 4;
static SW_TX_RING: StaticCell<[u32; TX_RING_BYTES]> = StaticCell::new();
static SW_RX_RING: StaticCell<[u8; RX_RING_BYTES]> = StaticCell::new();
static mut RX_PIN: Option<Input<'static>> = None;
#[embassy_executor::main]
async fn main(spawner: Spawner) {
info!("boot");
let mut config = CPUConfig::default();
config.rcc.hsi = true;
config.rcc.sys = Sysclk::PLL1_R;
config.rcc.pll1 = Some(Pll {
source: PllSource::HSI,
// 16 MHz / 1 × 20 / 2 = 160 MHz
prediv: PllPreDiv::DIV1,
mul: PllMul::MUL20,
divp: None,
divq: None,
divr: Some(PllDiv::DIV2),
});
config.enable_independent_io_supply = true;
config.enable_independent_analog_supply = true;
let p = embassy_stm32::init(config);
let f_tim7 = rcc::frequency::<embassy_stm32::peripherals::TIM7>().0;
info!("TIM7 clock after PLL config = {} Hz", f_tim7);
let f_tim6 = rcc::frequency::<embassy_stm32::peripherals::TIM6>().0;
info!("TIM6 clock after PLL config = {} Hz", f_tim6);
// HARDWARE UART to the PC
let mut cfg = Config::default();
cfg.baudrate = BAUD;
static TX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
static RX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
let uart = BufferedUart::new(
p.USART1,
p.PA10, // RX pin
p.PA9, // TX pin
TX_BUF.init([0; 256]),
RX_BUF.init([0; 256]),
Irqs,
cfg,
).unwrap();
let yield_period = usart1::setup_and_spawn(BAUD);
spawner.spawn(uart_task(uart, &PIPE_HW_TX, &PIPE_HW_RX).unwrap());
// END OF HARDWARE UART to the PC
// INTERNAL HARDWARE UART (USART2)
let mut cfg2 = Config::default();
cfg2.baudrate = BAUD;
static TX_BUF2: StaticCell<[u8; 256]> = StaticCell::new();
static RX_BUF2: StaticCell<[u8; 256]> = StaticCell::new();
let uart2 = BufferedUart::new(
p.USART2,
p.PA3, // RX
p.PA2, // TX
TX_BUF2.init([0; 256]),
RX_BUF2.init([0; 256]),
Irqs2,
cfg2,
).unwrap();
let yield_period2 = usart2::setup_and_spawn(BAUD);
spawner.spawn(uart_task_internal(uart2, &PIPE_INT_TX, &PIPE_INT_RX).unwrap());
info!("USART2 ready");
// END OF INTERNAL HARDWARE UART (USART2)
// USART1 <-> USART2 bridge
spawner.spawn(bridge_usart1_rx_to_usart2_tx(&PIPE_HW_RX, &PIPE_INT_TX).unwrap());
spawner.spawn(bridge_usart2_rx_to_usart1_tx(&PIPE_INT_RX, &PIPE_HW_TX).unwrap());
info!("USART1 <-> USART2 bridge active");
// END OF USART1 <-> USART2 bridge
// SOFTWARE UART
let rx_pin = Input::new(p.PD6, Pull::Up);
unsafe { RX_PIN = Some(rx_pin) };
let mut tx_pin = Output::new(p.PB0, Level::High, Speed::VeryHigh);
init_tim6_for_uart(p.TIM6, BAUD, TX_OVERSAMPLE);
init_tim7_for_uart(p.TIM7, BAUD, RX_OVERSAMPLE);
dump_tim6_regs();
let bsrr_ptr = embassy_stm32::pac::GPIOB.bsrr().as_ptr() as *mut u32; // POZOR B REGISTER
spawner.spawn(tx_dma_task(p.GPDMA1_CH0, bsrr_ptr, SW_TX_RING.init([0; TX_RING_BYTES]), &PIPE_SW_TX).unwrap());
// EDN OF SOFTWARE UART
let rx_ring = SW_RX_RING.init([0u8; RX_RING_BYTES]);
let gpio_idr = embassy_stm32::pac::GPIOD.idr().as_ptr() as *mut u8;
spawner.spawn(rx_dma_task(p.GPDMA1_CH1, gpio_idr, rx_ring, &PIPE_SW_RX).unwrap());
info!("SW UART RX DMA started");
let mut buf = [0u8; 64];
loop {
let n = PIPE_SW_RX.read(&mut buf).await;
if n > 0 {
let _ = PIPE_SW_TX.write(&buf[..n]).await;
// info!("SW UART decoded: {:a}", &buf[..n]);
}
yield_now().await;
}
}
#[embassy_executor::task]
pub async fn bridge_usart1_rx_to_usart2_tx(
usart1_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
usart2_tx: &'static Pipe<CriticalSectionRawMutex, 1024>,
) {
let mut buf = [0u8; 64];
loop {
let n = usart1_rx.read(&mut buf).await;
if n > 0 {
let _ = usart2_tx.write(&buf[..n]).await;
// info!("bridge USART1 - USART2 sent:{} bytes: {}", n, &buf[..n]);
}
yield_now().await;
}
}
#[embassy_executor::task]
pub async fn bridge_usart2_rx_to_usart1_tx(
usart2_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
usart1_tx: &'static Pipe<CriticalSectionRawMutex, 1024>,
) {
let mut buf = [0u8; 64];
loop {
let n = usart2_rx.read(&mut buf).await;
if n > 0 {
let _ = usart1_tx.write(&buf[..n]).await;
// info!("bridge: USART2 -> USART1 sent {} bytes", n);
}
yield_now().await;
}
}

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semestralka_1_final_lib/src/config.rs Normal file
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// src/config.rs
use crate::software_uart::uart_emulation::{Parity, StopBits, UartConfig};
use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
use embassy_sync::pipe::Pipe;
pub const BAUD: u32 = 9_600;
// pub const TX_PIN_BIT: u8 = 2; // PA2
// pub const RX_PIN_BIT: u8 = 3; // PA3
pub const TX_PIN_BIT: u8 = 0; // PB2
pub const RX_PIN_BIT: u8 = 6; // PC3
pub const TX_OVERSAMPLE: u16 = 1;
pub const RX_OVERSAMPLE: u16 = 13;
pub const RX_RING_BYTES: usize = 32768;
pub const TX_RING_BYTES: usize = 4096;
pub const PIPE_HW_TX_SIZE: usize = 1024;
pub const PIPE_HW_RX_SIZE: usize = 1024;
pub const PIPE_SW_TX_SIZE: usize = 1024;
pub const PIPE_SW_RX_SIZE: usize = 4096;
pub const PIPE_INT_TX_SIZE: usize = 1024;
pub const PIPE_INT_RX_SIZE: usize = 1024;
pub static PIPE_HW_TX: Pipe<CriticalSectionRawMutex, PIPE_HW_TX_SIZE> = Pipe::new();
pub static PIPE_HW_RX: Pipe<CriticalSectionRawMutex, PIPE_HW_RX_SIZE> = Pipe::new();
pub static PIPE_SW_TX: Pipe<CriticalSectionRawMutex, PIPE_SW_TX_SIZE> = Pipe::new();
pub static PIPE_SW_RX: Pipe<CriticalSectionRawMutex, PIPE_SW_RX_SIZE> = Pipe::new();
pub static PIPE_INT_TX: Pipe<CriticalSectionRawMutex, PIPE_INT_TX_SIZE> = Pipe::new();
pub static PIPE_INT_RX: Pipe<CriticalSectionRawMutex, PIPE_INT_RX_SIZE> = Pipe::new();
pub const UART_CFG: UartConfig = UartConfig {
data_bits: 8,
parity: Parity::None,
stop_bits: StopBits::One,
};

41
semestralka_1_final_lib/src/hw_uart_internal/driver.rs Normal file
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// src/hw_uart_internal/driver.rs
use defmt::unwrap;
use embassy_futures::select::{select, Either};
use embassy_stm32::usart::BufferedUart;
use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
use embassy_sync::pipe::Pipe;
use embedded_io_async::{Read, Write};
use crate::hw_uart_pc::safety::{RX_PIPE_CAP, TX_PIPE_CAP};
use embassy_futures::yield_now;
#[embassy_executor::task]
pub async fn uart_task(
mut uart: BufferedUart<'static>,
tx_pipe: &'static Pipe<CriticalSectionRawMutex, TX_PIPE_CAP>,
rx_pipe: &'static Pipe<CriticalSectionRawMutex, RX_PIPE_CAP>,
) {
let mut rx_byte = [0u8; 1];
let mut tx_buf = [0u8; 64];
loop {
let rx_fut = uart.read(&mut rx_byte);
let tx_fut = async {
let n = tx_pipe.read(&mut tx_buf).await;
n
};
match select(rx_fut, tx_fut).await {
// Incoming data from UART hardware
Either::First(res) => {
if let Ok(_) = res {
let _ = rx_pipe.write(&rx_byte).await;
}
}
// Outgoing data waiting in TX pipe
Either::Second(n) => {
unwrap!(uart.write(&tx_buf[..n]).await);
}
}
yield_now().await;
}
}

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semestralka_1_final_lib/src/hw_uart_internal/mod.rs Normal file
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// src/hw_uart_internal/mod.rs
pub mod driver;
pub mod usart2;

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semestralka_1_final_lib/src/hw_uart_internal/usart2.rs Normal file
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// src/hw_uart_internal/usart2.rs
use defmt::info;
use embassy_time::Duration;
use crate::hw_uart_pc::safety::preflight_and_suggest_yield_period;
pub fn setup_and_spawn(baudrate: u32) -> Duration {
let yield_period = preflight_and_suggest_yield_period(baudrate);
info!("HW USART2 safe");
yield_period
}

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semestralka_1_final_lib/src/hw_uart_pc/driver.rs Normal file
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// src/hw_uart_pc/driver.rs
use defmt::unwrap;
use embassy_futures::select::{select, Either};
use embassy_stm32::usart::BufferedUart;
use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
use embassy_sync::pipe::Pipe;
use embedded_io_async::{Read, Write};
use crate::hw_uart_pc::safety::{RX_PIPE_CAP, TX_PIPE_CAP};
use embassy_futures::yield_now;
#[embassy_executor::task]
pub async fn uart_task(
mut uart: BufferedUart<'static>,
tx_pipe: &'static Pipe<CriticalSectionRawMutex, TX_PIPE_CAP>,
rx_pipe: &'static Pipe<CriticalSectionRawMutex, RX_PIPE_CAP>,
) {
let mut rx_byte = [0u8; 1];
let mut tx_buf = [0u8; 64];
loop {
let rx_fut = uart.read(&mut rx_byte);
let tx_fut = async {
let n = tx_pipe.read(&mut tx_buf).await;
n
};
match select(rx_fut, tx_fut).await {
// Incoming data from UART hardware
Either::First(res) => {
if let Ok(_) = res {
let _ = rx_pipe.write(&rx_byte).await;
}
}
// Outgoing data waiting in TX pipe
Either::Second(n) => {
unwrap!(uart.write(&tx_buf[..n]).await);
}
}
yield_now().await;
}
}

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semestralka_1_final_lib/src/hw_uart_pc/mod.rs Normal file
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// src/hw_uart_pc/mod.rs
pub mod driver;
pub mod usart1;
pub mod safety;

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semestralka_1_final_lib/src/hw_uart_pc/safety.rs Normal file
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// src/safety.rs
use defmt::info;
use embassy_time::Duration;
// ISR RX ring capacity = RX_BUF len
const ISR_RX_BUF_CAP: usize = 256;
// Yield 1/2 the time it takes to fill ISR RX ring.
const YIELD_MARGIN_NUM: u32 = 1;
const YIELD_MARGIN_DEN: u32 = 2;
// Ensure RX_PIPE_CAP can hold this.
const WORST_MAIN_LATENCY_MS: u32 = 20;
pub const TX_PIPE_CAP: usize = 1024;
pub const RX_PIPE_CAP: usize = 1024;
/// Perform safety checks and compute yield timing to avoid buffer overflow.
///
/// # Panics
/// Panics if pipe capacities are too small for the configured baud.
pub fn preflight_and_suggest_yield_period(baud: u32) -> Duration {
// Approx bytes per second for 8N1 (10 bits per byte on the wire)
let bytes_per_sec = (baud / 10).max(1);
// Time until ISR RX ring fills, in microseconds.
let t_fill_us = (ISR_RX_BUF_CAP as u64) * 1_000_000u64 / (bytes_per_sec as u64);
// Choose a yield period as a fraction of t_fill.
let yield_us = (t_fill_us as u64)
.saturating_mul(YIELD_MARGIN_NUM as u64)
/ (YIELD_MARGIN_DEN as u64);
// Verify RX pipe can absorb a worst-case app latency so uart_task
// can always forward without dropping when it runs.
let required_rx_pipe = (bytes_per_sec as u64) * (WORST_MAIN_LATENCY_MS as u64) / 1000;
if (RX_PIPE_CAP as u64) < required_rx_pipe {
core::panic!(
"RX pipe too small: have {}B, need >= {}B for {}ms at {} bps",
RX_PIPE_CAP, required_rx_pipe, WORST_MAIN_LATENCY_MS, baud
);
}
info!(
"Preflight: baud={}, rx_isr={}B, rx_pipe={}B, bytes/s={}, t_fill_us={}, yield_us={}",
baud,
ISR_RX_BUF_CAP,
RX_PIPE_CAP,
bytes_per_sec,
t_fill_us,
yield_us
);
// Never choose zero.
Duration::from_micros(yield_us.max(1) as u64)
}

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semestralka_1_final_lib/src/hw_uart_pc/usart1.rs Normal file
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// src/uart/usart1.rs
use defmt::info;
use embassy_time::Duration;
use crate::hw_uart_pc::safety::preflight_and_suggest_yield_period;
pub fn setup_and_spawn(baudrate: u32,) -> Duration {
let yield_period: Duration = preflight_and_suggest_yield_period(baudrate);
info!("HW USART1 safe");
yield_period
}

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#![no_std]
pub mod config;
pub mod hw_uart_pc;
pub mod hw_uart_internal;

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#![no_std]
#![no_main]
use dma_gpio as _;
use panic_probe as _;
use defmt_rtt as _;
#[defmt_test::tests]
mod tests {
use defmt::assert_eq;
use dma_gpio::software_uart::uart_emulation::{
encode_uart_byte_cfg, UartConfig, Parity, StopBits
};
const TX_PIN_BIT: u8 = 2;
#[test]
fn test_encode_8n1() {
let cfg = UartConfig::default();
let mut frame = [0u32; 12];
let used = encode_uart_byte_cfg(TX_PIN_BIT, 0x55, &cfg, &mut frame);
assert_eq!(used, 10);
assert_eq!(frame[0], 1u32 << 18); // Start LOW
assert_eq!(frame[9], 1u32 << 2); // Stop HIGH
}
#[test]
fn test_encode_parity() {
let cfg = UartConfig {
data_bits: 8,
parity: Parity::Even,
stop_bits: StopBits::One,
};
let mut frame = [0u32; 12];
let used = encode_uart_byte_cfg(TX_PIN_BIT, 0x00, &cfg, &mut frame);
assert_eq!(used, 11);
}
}