software uart is now a library

semestralka_1_final_lib/src/bin/main.rs

@@ -0,0 +1,190 @@
+// src/bin/main.rs
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use core::cell::RefCell;
+use cortex_m::interrupt::Mutex;
+use embassy_executor::Spawner;
+use embassy_futures::yield_now;
+use embassy_sync::{
+    blocking_mutex::raw::CriticalSectionRawMutex,
+    channel::Channel,
+    pipe::Pipe,
+};
+use embassy_time::{Duration, Instant, Timer};
+use embassy_stm32::{
+    bind_interrupts,
+    dma::Request,
+    gpio::{Input, Level, Output, Pull, Speed},
+    interrupt,
+    pac,
+    peripherals,
+    rcc::{self, Pll, PllDiv, PllMul, PllPreDiv, PllSource, Sysclk},
+    usart::{BufferedInterruptHandler, BufferedUart, Config},
+    Config as CPUConfig,
+};
+use static_cell::StaticCell;
+use dma_gpio::config::{
+    BAUD, PIPE_HW_RX, PIPE_HW_TX, PIPE_INT_RX, PIPE_INT_TX, PIPE_SW_RX,
+    PIPE_SW_TX, RX_OVERSAMPLE, RX_RING_BYTES, TX_OVERSAMPLE, TX_RING_BYTES,
+    UART_CFG,
+};
+use dma_gpio::hw_uart_pc::{driver::uart_task, usart1};
+use dma_gpio::hw_uart_internal::{
+    driver::uart_task as uart_task_internal,
+    usart2,
+};
+use dma_gpio::software_uart::{
+    debug::dump_tim6_regs,
+    decode_uart_samples,
+    dma_timer::{init_tim6_for_uart, init_tim7_for_uart},
+    gpio_dma_uart_rx::rx_dma_task,
+    gpio_dma_uart_tx::tx_dma_task,
+};
+use {defmt_rtt as _, panic_probe as _};
+
+static PD6_BITS: Channel<CriticalSectionRawMutex, u8, 16384> = Channel::new();
+
+bind_interrupts!(struct Irqs {
+    USART1 => BufferedInterruptHandler<peripherals::USART1>;
+});
+bind_interrupts!(struct Irqs2 {
+    USART2 => BufferedInterruptHandler<peripherals::USART2>;
+});
+
+// Software uart
+pub const TIM6_UP_REQ: Request = 4;
+static SW_TX_RING: StaticCell<[u32; TX_RING_BYTES]> = StaticCell::new();
+static SW_RX_RING: StaticCell<[u8; RX_RING_BYTES]> = StaticCell::new();
+static mut RX_PIN: Option<Input<'static>> = None;
+
+#[embassy_executor::main]
+async fn main(spawner: Spawner) {
+    info!("boot");
+    let mut config = CPUConfig::default();
+    config.rcc.hsi = true;
+    config.rcc.sys = Sysclk::PLL1_R;
+    config.rcc.pll1 = Some(Pll {
+        source: PllSource::HSI,
+        // 16 MHz / 1 × 20 / 2 = 160 MHz
+        prediv: PllPreDiv::DIV1,
+        mul:    PllMul::MUL20,
+        divp:   None,
+        divq:   None,
+        divr:   Some(PllDiv::DIV2),
+    });
+    config.enable_independent_io_supply = true;
+    config.enable_independent_analog_supply = true;
+
+    let p = embassy_stm32::init(config);
+    let f_tim7 = rcc::frequency::<embassy_stm32::peripherals::TIM7>().0;
+    info!("TIM7 clock after PLL config = {} Hz", f_tim7);
+    let f_tim6 = rcc::frequency::<embassy_stm32::peripherals::TIM6>().0;
+    info!("TIM6 clock after PLL config = {} Hz", f_tim6);
+
+    // HARDWARE UART to the PC
+    let mut cfg = Config::default();
+    cfg.baudrate = BAUD;
+    static TX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
+    static RX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
+    let uart = BufferedUart::new(
+        p.USART1,
+        p.PA10, // RX pin
+        p.PA9,  // TX pin
+        TX_BUF.init([0; 256]),
+        RX_BUF.init([0; 256]),
+        Irqs,
+        cfg,
+    ).unwrap();
+    let yield_period = usart1::setup_and_spawn(BAUD);
+    spawner.spawn(uart_task(uart, &PIPE_HW_TX, &PIPE_HW_RX).unwrap());
+    // END OF HARDWARE UART to the PC
+
+    // INTERNAL HARDWARE UART (USART2)
+    let mut cfg2 = Config::default();
+    cfg2.baudrate = BAUD;
+    static TX_BUF2: StaticCell<[u8; 256]> = StaticCell::new();
+    static RX_BUF2: StaticCell<[u8; 256]> = StaticCell::new();
+
+    let uart2 = BufferedUart::new(
+        p.USART2,
+        p.PA3, // RX
+        p.PA2, // TX
+        TX_BUF2.init([0; 256]),
+        RX_BUF2.init([0; 256]),
+        Irqs2,
+        cfg2,
+    ).unwrap();
+    let yield_period2 = usart2::setup_and_spawn(BAUD);
+    spawner.spawn(uart_task_internal(uart2, &PIPE_INT_TX, &PIPE_INT_RX).unwrap());
+    info!("USART2 ready");
+    // END OF INTERNAL HARDWARE UART (USART2)
+    
+    // USART1 <-> USART2 bridge
+    spawner.spawn(bridge_usart1_rx_to_usart2_tx(&PIPE_HW_RX, &PIPE_INT_TX).unwrap());
+    spawner.spawn(bridge_usart2_rx_to_usart1_tx(&PIPE_INT_RX, &PIPE_HW_TX).unwrap());
+    info!("USART1 <-> USART2 bridge active");
+    // END OF USART1 <-> USART2 bridge 
+
+    // SOFTWARE UART 
+    let rx_pin = Input::new(p.PD6, Pull::Up);
+    unsafe { RX_PIN = Some(rx_pin) };
+
+    let mut tx_pin = Output::new(p.PB0, Level::High, Speed::VeryHigh);
+    init_tim6_for_uart(p.TIM6, BAUD, TX_OVERSAMPLE);
+    init_tim7_for_uart(p.TIM7, BAUD, RX_OVERSAMPLE);
+    dump_tim6_regs();
+
+    let bsrr_ptr = embassy_stm32::pac::GPIOB.bsrr().as_ptr() as *mut u32; // POZOR B REGISTER
+    spawner.spawn(tx_dma_task(p.GPDMA1_CH0, bsrr_ptr, SW_TX_RING.init([0; TX_RING_BYTES]), &PIPE_SW_TX).unwrap());
+    // EDN OF SOFTWARE UART
+
+
+    let rx_ring = SW_RX_RING.init([0u8; RX_RING_BYTES]);
+    let gpio_idr = embassy_stm32::pac::GPIOD.idr().as_ptr() as *mut u8;
+    spawner.spawn(rx_dma_task(p.GPDMA1_CH1, gpio_idr, rx_ring, &PIPE_SW_RX).unwrap());
+    info!("SW UART RX DMA started");
+
+    let mut buf = [0u8; 64];
+    loop {
+        let n = PIPE_SW_RX.read(&mut buf).await;
+        if n > 0 {
+            let _ = PIPE_SW_TX.write(&buf[..n]).await;
+            // info!("SW UART decoded: {:a}", &buf[..n]);
+        }
+        yield_now().await;
+    }
+}
+
+#[embassy_executor::task]
+pub async fn bridge_usart1_rx_to_usart2_tx(
+    usart1_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+    usart2_tx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    let mut buf = [0u8; 64];
+    loop {
+        let n = usart1_rx.read(&mut buf).await;
+        if n > 0 {
+            let _ = usart2_tx.write(&buf[..n]).await;
+            // info!("bridge USART1 - USART2 sent:{} bytes: {}", n, &buf[..n]);
+        }
+        yield_now().await;
+    }
+}
+
+#[embassy_executor::task]
+pub async fn bridge_usart2_rx_to_usart1_tx(
+    usart2_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+    usart1_tx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    let mut buf = [0u8; 64];
+    loop {
+        let n = usart2_rx.read(&mut buf).await;
+        if n > 0 {
+            let _ = usart1_tx.write(&buf[..n]).await;
+            // info!("bridge: USART2 -> USART1 sent {} bytes", n);
+        }
+        yield_now().await;
+    }
+}

semestralka_1_final_lib/src/config.rs

@@ -0,0 +1,35 @@
+// src/config.rs
+use crate::software_uart::uart_emulation::{Parity, StopBits, UartConfig};
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use embassy_sync::pipe::Pipe;
+
+pub const BAUD: u32 = 9_600;
+// pub const TX_PIN_BIT: u8 = 2; // PA2
+// pub const RX_PIN_BIT: u8 = 3; // PA3
+pub const TX_PIN_BIT: u8 = 0; // PB2
+pub const RX_PIN_BIT: u8 = 6; // PC3
+pub const TX_OVERSAMPLE: u16 = 1;
+pub const RX_OVERSAMPLE: u16 = 13;
+
+pub const RX_RING_BYTES: usize = 32768;
+pub const TX_RING_BYTES: usize = 4096;
+
+pub const PIPE_HW_TX_SIZE: usize = 1024;
+pub const PIPE_HW_RX_SIZE: usize = 1024;
+pub const PIPE_SW_TX_SIZE: usize = 1024;
+pub const PIPE_SW_RX_SIZE: usize = 4096;
+pub const PIPE_INT_TX_SIZE: usize = 1024;
+pub const PIPE_INT_RX_SIZE: usize = 1024;
+
+pub static PIPE_HW_TX: Pipe<CriticalSectionRawMutex, PIPE_HW_TX_SIZE> = Pipe::new();
+pub static PIPE_HW_RX: Pipe<CriticalSectionRawMutex, PIPE_HW_RX_SIZE> = Pipe::new();
+pub static PIPE_SW_TX: Pipe<CriticalSectionRawMutex, PIPE_SW_TX_SIZE> = Pipe::new();
+pub static PIPE_SW_RX: Pipe<CriticalSectionRawMutex, PIPE_SW_RX_SIZE> = Pipe::new();
+pub static PIPE_INT_TX: Pipe<CriticalSectionRawMutex, PIPE_INT_TX_SIZE> = Pipe::new();
+pub static PIPE_INT_RX: Pipe<CriticalSectionRawMutex, PIPE_INT_RX_SIZE> = Pipe::new();
+
+pub const UART_CFG: UartConfig = UartConfig {
+    data_bits: 8,
+    parity: Parity::None,
+    stop_bits: StopBits::One,
+};

semestralka_1_final_lib/src/hw_uart_internal/driver.rs

@@ -0,0 +1,41 @@
+// src/hw_uart_internal/driver.rs
+use defmt::unwrap;
+use embassy_futures::select::{select, Either};
+use embassy_stm32::usart::BufferedUart;
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use embassy_sync::pipe::Pipe;
+use embedded_io_async::{Read, Write};
+use crate::hw_uart_pc::safety::{RX_PIPE_CAP, TX_PIPE_CAP};
+use embassy_futures::yield_now;
+
+#[embassy_executor::task]
+pub async fn uart_task(
+    mut uart: BufferedUart<'static>,
+    tx_pipe: &'static Pipe<CriticalSectionRawMutex, TX_PIPE_CAP>,
+    rx_pipe: &'static Pipe<CriticalSectionRawMutex, RX_PIPE_CAP>,
+) {
+    let mut rx_byte = [0u8; 1];
+    let mut tx_buf = [0u8; 64];
+
+    loop {
+        let rx_fut = uart.read(&mut rx_byte);
+        let tx_fut = async {
+            let n = tx_pipe.read(&mut tx_buf).await;
+            n
+        };
+
+        match select(rx_fut, tx_fut).await {
+            // Incoming data from UART hardware
+            Either::First(res) => {
+                if let Ok(_) = res {
+                    let _ = rx_pipe.write(&rx_byte).await;
+                }
+            }
+            // Outgoing data waiting in TX pipe
+            Either::Second(n) => {
+                unwrap!(uart.write(&tx_buf[..n]).await);
+            }
+        }
+        yield_now().await;
+    }
+}

semestralka_1_final_lib/src/hw_uart_internal/mod.rs

@@ -0,0 +1,4 @@
+// src/hw_uart_internal/mod.rs
+
+pub mod driver;
+pub mod usart2;

semestralka_1_final_lib/src/hw_uart_internal/usart2.rs

@@ -0,0 +1,11 @@
+// src/hw_uart_internal/usart2.rs
+use defmt::info;
+use embassy_time::Duration;
+
+use crate::hw_uart_pc::safety::preflight_and_suggest_yield_period;
+
+pub fn setup_and_spawn(baudrate: u32) -> Duration {
+    let yield_period = preflight_and_suggest_yield_period(baudrate);
+    info!("HW USART2 safe");
+    yield_period
+}

semestralka_1_final_lib/src/hw_uart_pc/driver.rs

@@ -0,0 +1,41 @@
+// src/hw_uart_pc/driver.rs
+use defmt::unwrap;
+use embassy_futures::select::{select, Either};
+use embassy_stm32::usart::BufferedUart;
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use embassy_sync::pipe::Pipe;
+use embedded_io_async::{Read, Write};
+use crate::hw_uart_pc::safety::{RX_PIPE_CAP, TX_PIPE_CAP};
+use embassy_futures::yield_now;
+
+#[embassy_executor::task]
+pub async fn uart_task(
+    mut uart: BufferedUart<'static>,
+    tx_pipe: &'static Pipe<CriticalSectionRawMutex, TX_PIPE_CAP>,
+    rx_pipe: &'static Pipe<CriticalSectionRawMutex, RX_PIPE_CAP>,
+) {
+    let mut rx_byte = [0u8; 1];
+    let mut tx_buf = [0u8; 64];
+
+    loop {
+        let rx_fut = uart.read(&mut rx_byte);
+        let tx_fut = async {
+            let n = tx_pipe.read(&mut tx_buf).await;
+            n
+        };
+
+        match select(rx_fut, tx_fut).await {
+            // Incoming data from UART hardware
+            Either::First(res) => {
+                if let Ok(_) = res {
+                    let _ = rx_pipe.write(&rx_byte).await;
+                }
+            }
+            // Outgoing data waiting in TX pipe
+            Either::Second(n) => {
+                unwrap!(uart.write(&tx_buf[..n]).await);
+            }
+        }
+        yield_now().await;
+    }
+}

semestralka_1_final_lib/src/hw_uart_pc/mod.rs

@@ -0,0 +1,4 @@
+// src/hw_uart_pc/mod.rs
+pub mod driver;
+pub mod usart1;
+pub mod safety;

semestralka_1_final_lib/src/hw_uart_pc/safety.rs

@@ -0,0 +1,57 @@
+// src/safety.rs
+use defmt::info;
+use embassy_time::Duration;
+
+// ISR RX ring capacity = RX_BUF len
+const ISR_RX_BUF_CAP: usize = 256;
+// Yield 1/2 the time it takes to fill ISR RX ring.
+const YIELD_MARGIN_NUM: u32 = 1;
+const YIELD_MARGIN_DEN: u32 = 2;
+// Ensure RX_PIPE_CAP can hold this.
+const WORST_MAIN_LATENCY_MS: u32 = 20;
+
+pub const TX_PIPE_CAP: usize = 1024;
+pub const RX_PIPE_CAP: usize = 1024;
+
+
+
+/// Perform safety checks and compute yield timing to avoid buffer overflow.
+///
+/// # Panics
+/// Panics if pipe capacities are too small for the configured baud.
+pub fn preflight_and_suggest_yield_period(baud: u32) -> Duration {
+    // Approx bytes per second for 8N1 (10 bits per byte on the wire)
+    let bytes_per_sec = (baud / 10).max(1);
+
+    // Time until ISR RX ring fills, in microseconds.
+    let t_fill_us = (ISR_RX_BUF_CAP as u64) * 1_000_000u64 / (bytes_per_sec as u64);
+
+    // Choose a yield period as a fraction of t_fill.
+    let yield_us = (t_fill_us as u64)
+        .saturating_mul(YIELD_MARGIN_NUM as u64)
+        / (YIELD_MARGIN_DEN as u64);
+
+    // Verify RX pipe can absorb a worst-case app latency so uart_task
+    // can always forward without dropping when it runs.
+    let required_rx_pipe = (bytes_per_sec as u64) * (WORST_MAIN_LATENCY_MS as u64) / 1000;
+
+    if (RX_PIPE_CAP as u64) < required_rx_pipe {
+        core::panic!(
+            "RX pipe too small: have {}B, need >= {}B for {}ms at {} bps",
+            RX_PIPE_CAP, required_rx_pipe, WORST_MAIN_LATENCY_MS, baud
+        );
+    }
+
+    info!(
+        "Preflight: baud={}, rx_isr={}B, rx_pipe={}B, bytes/s={}, t_fill_us={}, yield_us={}",
+        baud,
+        ISR_RX_BUF_CAP,
+        RX_PIPE_CAP,
+        bytes_per_sec,
+        t_fill_us,
+        yield_us
+    );
+
+    // Never choose zero.
+    Duration::from_micros(yield_us.max(1) as u64)
+}

semestralka_1_final_lib/src/hw_uart_pc/usart1.rs

@@ -0,0 +1,12 @@
+// src/uart/usart1.rs
+use defmt::info;
+use embassy_time::Duration;
+
+use crate::hw_uart_pc::safety::preflight_and_suggest_yield_period;
+
+pub fn setup_and_spawn(baudrate: u32,) -> Duration {
+    let yield_period: Duration = preflight_and_suggest_yield_period(baudrate);
+    info!("HW USART1 safe");
+
+    yield_period
+}

semestralka_1_final_lib/src/lib.rs

@@ -0,0 +1,5 @@
+#![no_std]
+
+pub mod config;
+pub mod hw_uart_pc;
+pub mod hw_uart_internal;