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working buffer transfer, lets build from in here

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Priec
2025-11-19 12:56:47 +01:00
parent da2f011682
commit 2ef75c319d
1 changed files with 0 additions and 17 deletions
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17
semestralka_1d_rx_bez_dma/src/bin/main.rs
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@@ -106,24 +106,7 @@ async fn main(spawner: Spawner) {
// EDN OF SOFTWARE UART // EDN OF SOFTWARE UART
let mut last_yield = Instant::now();
let mut buf = [0u8; 32];
let mut last_state: u8 = 0;
loop { loop {
// info!("tick start");
// Timer::after(Duration::from_millis(100)).await;
// info!("tick end");
// let n1 = PIPE_HW_RX.read(&mut buf).await;
// if n1 > 0 {
// info!("PC received: {:a}", &buf[..n1]);
// let _ = PIPE_SW_TX.write(&buf[..n1]).await;
// info!("SW UART TX sent echo: {:a}", &buf[..n1]);
// }
// yield_now().await;
yield_now().await; yield_now().await;
} }
} }