filipriec/stm32_rust
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starting fresh again 1d rx bez dma

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This commit is contained in:
Priec
2025-11-19 13:03:28 +01:00
parent 2ef75c319d
commit 28d041873c
2 changed files with 21 additions and 2 deletions
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18
semestralka_1d_rx_bez_dma/src/bin/main.rs
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@@ -28,8 +28,14 @@ use dma_gpio::hw_uart_internal::usart2;
use dma_gpio::hw_uart_internal::driver::uart_task as uart_task_internal; use dma_gpio::hw_uart_internal::driver::uart_task as uart_task_internal;
use dma_gpio::config::{PIPE_INT_TX, PIPE_INT_RX}; use dma_gpio::config::{PIPE_INT_TX, PIPE_INT_RX};
use embassy_time::{Duration, Timer}; use embassy_time::{Duration, Timer};
use embassy_stm32::pac;
use {defmt_rtt as _, panic_probe as _}; use {defmt_rtt as _, panic_probe as _};
use cortex_m::interrupt::Mutex;
use core::cell::RefCell;
static RX_PIN_GLOBAL: Mutex<RefCell<Option<&'static Input<'static>>>> = Mutex::new(RefCell::new(None));
bind_interrupts!(struct Irqs { bind_interrupts!(struct Irqs {
USART1 => BufferedInterruptHandler<peripherals::USART1>; USART1 => BufferedInterruptHandler<peripherals::USART1>;
}); });
@@ -82,7 +88,6 @@ async fn main(spawner: Spawner) {
Irqs2, Irqs2,
cfg2, cfg2,
).unwrap(); ).unwrap();
let _ = usart2::setup_and_spawn(BAUD); let _ = usart2::setup_and_spawn(BAUD);
spawner.spawn(uart_task_internal(uart2, &PIPE_INT_TX, &PIPE_INT_RX).unwrap()); spawner.spawn(uart_task_internal(uart2, &PIPE_INT_TX, &PIPE_INT_RX).unwrap());
info!("USART2 ready"); info!("USART2 ready");
@@ -97,15 +102,24 @@ async fn main(spawner: Spawner) {
// SOFTWARE UART // SOFTWARE UART
// let _rx = Input::new(p.PD6, Pull::Up); // let _rx = Input::new(p.PD6, Pull::Up);
let rx_pin = Input::new(p.PD6, Pull::Up); let rx_pin = Input::new(p.PD6, Pull::Up);
// Configure TX as output (PB0)
// Rx ready for the interrupt
use cortex_m::interrupt::free;
let rx_pin_ref: &'static Input<'static> = unsafe { core::mem::transmute(&rx_pin) };
free(|cs| RX_PIN_GLOBAL.borrow(cs).replace(Some(rx_pin_ref)));
// Configure TX as output (PB0)
let mut tx_pin = Output::new(p.PB0, Level::High, Speed::VeryHigh); let mut tx_pin = Output::new(p.PB0, Level::High, Speed::VeryHigh);
init_tim6_for_uart(p.TIM6, BAUD, TX_OVERSAMPLE); init_tim6_for_uart(p.TIM6, BAUD, TX_OVERSAMPLE);
init_tim7_for_uart(p.TIM7, BAUD, RX_OVERSAMPLE); init_tim7_for_uart(p.TIM7, BAUD, RX_OVERSAMPLE);
unsafe { cortex_m::peripheral::NVIC::unmask(pac::Interrupt::TIM7); }
info!("TIM7 Interrupt enabled");
dump_tim6_regs(); dump_tim6_regs();
// EDN OF SOFTWARE UART // EDN OF SOFTWARE UART
loop { loop {
yield_now().await; yield_now().await;
} }

5
semestralka_1d_rx_bez_dma/src/software_uart/dma_timer.rs
View File

@@ -25,6 +25,8 @@ pub fn init_tim7_for_uart<'d>(tim7: Peri<'d, TIM7>, baud: u32, oversample: u16)
rcc::enable_and_reset::<TIM7>(); rcc::enable_and_reset::<TIM7>();
let ll = Timer::new(tim7); let ll = Timer::new(tim7);
configure_basic_timer(&ll, baud, oversample); configure_basic_timer(&ll, baud, oversample);
// Enable Update Interrupt (UIE)
ll.regs_basic().dier().modify(|w| w.set_uie(true));
mem::forget(ll); mem::forget(ll);
} }
@@ -49,6 +51,9 @@ fn configure_basic_timer<T: BasicInstance>(ll: &Timer<'_, T>, baud: u32, oversam
ll.regs_basic().dier().modify(|w| w.set_ude(true)); ll.regs_basic().dier().modify(|w| w.set_ude(true));
ll.regs_basic().egr().write(|w| w.set_ug(true)); ll.regs_basic().egr().write(|w| w.set_ug(true));
// Clear spurious UIF from UG trigger
ll.regs_basic().sr().modify(|w| w.set_uif(false));
ll.regs_basic().cr1().write(|w| { ll.regs_basic().cr1().write(|w| {
w.set_opm(false); w.set_opm(false);
w.set_cen(true); w.set_cen(true);