starting fresh again 1d rx bez dma

semestralka_1d_rx_bez_dma/src/software_uart/dma_timer.rs

@@ -25,6 +25,8 @@ pub fn init_tim7_for_uart<'d>(tim7: Peri<'d, TIM7>, baud: u32, oversample: u16)
     rcc::enable_and_reset::<TIM7>();
     let ll = Timer::new(tim7);
     configure_basic_timer(&ll, baud, oversample);
+    // Enable Update Interrupt (UIE)
+    ll.regs_basic().dier().modify(|w| w.set_uie(true));
     mem::forget(ll);
 }
 
@@ -49,6 +51,9 @@ fn configure_basic_timer<T: BasicInstance>(ll: &Timer<'_, T>, baud: u32, oversam
     ll.regs_basic().dier().modify(|w| w.set_ude(true));
     ll.regs_basic().egr().write(|w| w.set_ug(true));
 
+    // Clear spurious UIF from UG trigger
+    ll.regs_basic().sr().modify(|w| w.set_uif(false));
+
     ll.regs_basic().cr1().write(|w| {
         w.set_opm(false);
         w.set_cen(true);