restored Rx ring properly well with the dma_gpio2 initialized

dma_gpio/src/software_uart/gpio_dma_uart_tx.rs

@@ -1,23 +1,28 @@
 // src/software_uart/gpio_dma_uart_tx.rs
-use embassy_stm32::dma::Request;
-use embassy_stm32::dma::WritableRingBuffer;
+use embassy_futures::yield_now;
 use crate::software_uart::uart_emulation::encode_uart_byte_cfg;
 use crate::config::UART_CFG;
 
-// kapitola 17.4.11 - 2 casovace pre 2 DMA
-pub const TIM6_UP_REQ: Request = 4; // Table 137: tim6_upd_dma, strana 687 STM32U5xx datasheet
-
-/// Push UART frames into the DMA-backed TX ring
-pub async fn write_uart_frames_to_ring(
-    ring: &mut WritableRingBuffer<'static, u32>,
+pub async fn encode_uart_frames<'a>(
     pin_bit: u8,
     bytes: &[u8],
-) {
+    out_buf: &'a mut [u32],
+) -> usize {
+    let mut offset = 0;
     for &b in bytes {
         let mut frame = [0u32; 12];
         let used = encode_uart_byte_cfg(pin_bit, b, &UART_CFG, &mut frame);
 
-        // Will wait until all words are written
-        ring.write_exact(&frame[..used]).await.unwrap();
+        if offset + used <= out_buf.len() {
+            out_buf[offset..offset + used].copy_from_slice(&frame[..used]);
+            offset += used;
+        } else {
+            break;
+        }
+
+        // cooperative async yield
+        yield_now().await;
     }
+    offset
 }
+