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restored Rx ring properly well with the dma_gpio2 initialized

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Filipriec
2025-11-10 18:11:28 +01:00
parent f4e59d977b
commit 25c6d3d265
2 changed files with 38 additions and 20 deletions
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31
dma_gpio/src/bin/main.rs
View File

@@ -4,24 +4,27 @@
use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::dma::Request;
use embassy_stm32::gpio::{Input, Output, Level, Pull, Speed};
use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
use embassy_time::{Duration, Timer};
use embassy_stm32::dma::{TransferOptions, WritableRingBuffer};
use dma_gpio::software_uart::{
dma_timer::{init_tim6_for_uart, init_tim7_for_uart},
gpio_dma_uart_tx::{write_uart_frames_to_ring, TIM6_UP_REQ},
gpio_dma_uart_tx::encode_uart_frames,
gpio_dma_uart_rx::rx_dma_task,
debug::dump_tim6_regs,
};
use dma_gpio::config::{BAUD, TX_PIN_BIT, RX_OVERSAMPLE, TX_OVERSAMPLE};
use dma_gpio::config::{TX_RING_BYTES, RX_RING_BYTES, PIPE_RX_SIZE};
use static_cell::StaticCell;
use embassy_futures::yield_now;
use {defmt_rtt as _, panic_probe as _};
pub const TIM6_UP_REQ: Request = 4;
static PIPE_RX: Pipe<CriticalSectionRawMutex, PIPE_RX_SIZE> = Pipe::new();
static RX_RING: StaticCell<[u8; RX_RING_BYTES]> = StaticCell::new();
static TX_RING: StaticCell<[u32; TX_RING_BYTES]> = StaticCell::new();
static RX_RING: StaticCell<[u8; RX_RING_BYTES]> = StaticCell::new();
#[embassy_executor::main]
async fn main(spawner: Spawner) {
@@ -64,16 +67,26 @@ async fn main(spawner: Spawner) {
tx_ring.start();
info!("TX DMA ring started");
let mut frame_buf = [0u32; 4096];
loop {
info!("tick start");
Timer::after(Duration::from_millis(100)).await;
info!("tick end");
write_uart_frames_to_ring(
&mut tx_ring,
// Timer::after(Duration::from_millis(100)).await;
// info!("tick end");
let used = encode_uart_frames(
TX_PIN_BIT,
b"Hello marshmallow\r\n",
).await;
&mut frame_buf,
)
.await;
if used == 0 {
info!("encode_uart_frames() produced 0 words, skipping write");
yield_now().await;
continue;
}
let _ = tx_ring.write_exact(&frame_buf[..used]).await;
info!("text");
Timer::after(Duration::from_secs(1)).await;
yield_now().await;
}
}

27
dma_gpio/src/software_uart/gpio_dma_uart_tx.rs
View File

@@ -1,23 +1,28 @@
// src/software_uart/gpio_dma_uart_tx.rs
use embassy_stm32::dma::Request;
use embassy_stm32::dma::WritableRingBuffer;
use embassy_futures::yield_now;
use crate::software_uart::uart_emulation::encode_uart_byte_cfg;
use crate::config::UART_CFG;
// kapitola 17.4.11 - 2 casovace pre 2 DMA
pub const TIM6_UP_REQ: Request = 4; // Table 137: tim6_upd_dma, strana 687 STM32U5xx datasheet
/// Push UART frames into the DMA-backed TX ring
pub async fn write_uart_frames_to_ring(
ring: &mut WritableRingBuffer<'static, u32>,
pub async fn encode_uart_frames<'a>(
pin_bit: u8,
bytes: &[u8],
) {
out_buf: &'a mut [u32],
) -> usize {
let mut offset = 0;
for &b in bytes {
let mut frame = [0u32; 12];
let used = encode_uart_byte_cfg(pin_bit, b, &UART_CFG, &mut frame);
// Will wait until all words are written
ring.write_exact(&frame[..used]).await.unwrap();
if offset + used <= out_buf.len() {
out_buf[offset..offset + used].copy_from_slice(&frame[..used]);
offset += used;
} else {
break;
}
// cooperative async yield
yield_now().await;
}
offset
}