compiled hw and sw uart in semestralka
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@@ -1,6 +1,5 @@
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// src/uart/driver.rs
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use defmt::unwrap;
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use embassy_executor::Spawner;
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use embassy_futures::select::{select, Either};
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use embassy_stm32::usart::BufferedUart;
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use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
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@@ -8,7 +7,7 @@ use embassy_sync::pipe::Pipe;
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use embassy_time::Duration;
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use embedded_io_async::{Read, Write};
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use crate::uart::safety::{RX_PIPE_CAP, TX_PIPE_CAP};
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use crate::hw_uart_pc::safety::{RX_PIPE_CAP, TX_PIPE_CAP};
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pub struct UartHandle {
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pub tx: &'static Pipe<CriticalSectionRawMutex, TX_PIPE_CAP>,
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@@ -36,9 +35,7 @@ pub async fn uart_task(
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// Incoming data from UART hardware
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Either::First(res) => {
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if let Ok(_) = res {
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// Forward to RX pipe and echo to TX pipe (same behavior as before)
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let _ = rx_pipe.write(&rx_byte).await;
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let _ = tx_pipe.try_write(&rx_byte);
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}
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}
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// Outgoing data waiting in TX pipe
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@@ -48,18 +45,3 @@ pub async fn uart_task(
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}
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}
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}
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pub fn spawn_for(
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spawner: &Spawner,
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uart: BufferedUart<'static>,
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tx_pipe: &'static Pipe<CriticalSectionRawMutex, TX_PIPE_CAP>,
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rx_pipe: &'static Pipe<CriticalSectionRawMutex, RX_PIPE_CAP>,
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yield_period: Duration,
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) -> UartHandle {
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spawner.spawn(uart_task(uart, tx_pipe, rx_pipe)).unwrap();
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UartHandle {
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tx: tx_pipe,
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rx: rx_pipe,
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yield_period,
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}
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}
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