finished and fully functional

semestralka_1_connected/src/software_uart/gpio_dma_uart_tx.rs

@@ -1,7 +1,7 @@
 // src/software_uart/gpio_dma_uart_tx.rs
 use embassy_executor::task;
 use embassy_stm32::{
-    dma::{Request, TransferOptions, WritableRingBuffer},
+    dma::{Request, Transfer, TransferOptions},
     peripherals::GPDMA1_CH0,
     Peri,
 };
@@ -32,40 +32,23 @@ pub async fn encode_uart_frames<'a>(
             break;
         }
 
-        // cooperative async yield
         yield_now().await;
     }
     offset
 }
 
-/// TX DMA task: encodes UART frames and sends them via DMA at TIM6 rate
 #[task]
 pub async fn tx_dma_task(
-    ch: Peri<'static, GPDMA1_CH0>,
-    register: *mut u32, // Either odr or bsrr
-    tx_ring_mem: &'static mut [u32],
+    mut ch: Peri<'static, GPDMA1_CH0>,
+    register: *mut u32, // GPIOx_BSRR
+    _tx_ring_mem: &'static mut [u32],
     pipe_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
 ) {
-    let mut tx_opts = TransferOptions::default();
-    tx_opts.half_transfer_ir = true;
-    tx_opts.complete_transfer_ir = true;
-
-    // SAFETY: tx_ring is exclusive to this task
-    let mut tx_ring = unsafe {
-        WritableRingBuffer::new(
-            ch,
-            TIM6_UP_REQ,
-            register,
-            tx_ring_mem,
-            tx_opts,
-        )
-    };
-
-    tx_ring.start();
-    info!("TX DMA ring started");
+    info!("TX DMA task ready (One‑shot)");
 
     let mut frame_buf = [0u32; 4096];
     let mut rx_buf = [0u8; 256];
+    let tim6 = embassy_stm32::pac::TIM6;
 
     loop {
         let n = pipe_rx.read(&mut rx_buf).await;
@@ -76,9 +59,33 @@ pub async fn tx_dma_task(
 
         let used = encode_uart_frames(TX_PIN_BIT, &rx_buf[..n], &mut frame_buf).await;
         if used > 0 {
-            let _ = tx_ring.write_exact(&frame_buf[..used]).await;
+            // Align arming to a clean TIM6 update boundary:
+            // 1) clear any pending UIF
+            tim6.sr().write(|w| w.set_uif(false));
+            // 2) wait for the next UIF (next bit tick)
+            while !tim6.sr().read().uif() {
+                yield_now().await;
+            }
+            // 3) clear UIF so first DMA beat happens on the FOLLOWING tick
+            tim6.sr().write(|w| w.set_uif(false));
+
+            let mut tx_opts = TransferOptions::default();
+            tx_opts.half_transfer_ir = false;
+            tx_opts.complete_transfer_ir = true;
+
+            unsafe {
+                let transfer = Transfer::new_write(
+                    ch.reborrow(),
+                    TIM6_UP_REQ,
+                    &frame_buf[..used],
+                    register,
+                    tx_opts,
+                );
+                transfer.await;
+            }
         }
-        info!("tx_dma_task wrote {} words", used);
+
+        // info!("tx_dma_task sent {} words", used);
         yield_now().await;
     }
 }