compiled and working

dma_gpio/src/software_uart/runtime.rs

@@ -9,39 +9,47 @@ use embassy_stm32::{
 use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
 use embassy_time::Duration;
 use crate::software_uart::{
-    gpio_dma_uart_rx::TIM7_UP_REQ, gpio_dma_uart_tx::GpioDmaBsrrTx,
+    gpio_dma_uart_rx::TIM7_UP_REQ,
+    gpio_dma_uart_tx::GpioDmaBsrrTx,
     debug::{dump_dma_ch0_regs, dump_tim6_regs},
 };
 
 /// RX DMA task: reads GPIO samples paced by TIM7 and fills PIPE_RX
 #[task]
-pub async fn rx_dma_task(ch: Peri<'static, GPDMA1_CH1>) {
-    let ring = unsafe { &mut RX_RING };
+pub async fn rx_dma_task(
+    ch: Peri<'static, GPDMA1_CH1>,
+    pipe_rx: &'static Pipe<CriticalSectionRawMutex, 256>,
+    ring: &'static mut [u8],
+) {
     let gpioa_idr = embassy_stm32::pac::GPIOA.idr().as_ptr() as *mut u8;
 
     let mut opts = TransferOptions::default();
     opts.half_transfer_ir = true;
     opts.complete_transfer_ir = true;
 
+    // SAFETY: ring is exclusive to this task
     let mut rx = unsafe { DmaRingRx::new(ch, TIM7_UP_REQ, gpioa_idr, ring, opts) };
     rx.start();
 
     let mut chunk = [0u8; 256];
     loop {
         let _ = rx.read_exact(&mut chunk).await;
-        PIPE_RX.write(&chunk).await;
+        pipe_rx.write(&chunk).await;
     }
 }
 
 /// TX DMA task: dequeues prebuilt frames from PIPE_TX and writes to GPIOA.BSRR
 #[task]
-pub async fn tx_dma_task(ch: Peri<'static, GPDMA1_CH0>) {
+pub async fn tx_dma_task(
+    ch: Peri<'static, GPDMA1_CH0>,
+    pipe_tx: &'static Pipe<CriticalSectionRawMutex, 256>,
+) {
     let mut tx = GpioDmaBsrrTx::new(ch);
     info!("DMA TX task started");
 
     loop {
         let mut b = [0u8; 4];
-        let n = PIPE_TX.read(&mut b).await;
+        let n = pipe_tx.read(&mut b).await;
         if n != 4 {
             continue;
         }