filipriec/stm32_rust
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

debugging more

Browse Source
This commit is contained in:
Filipriec
2025-11-18 16:55:42 +01:00
parent 1909497403
commit 0a0ff0f38a
58 changed files with 5642 additions and 30 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
semestralka_1f_rx_bez_dma_toggle/src/bin/main.rs
View File

@@ -111,8 +111,8 @@ async fn main(spawner: Spawner) {
let mut last_state: u8 = 0;
loop {
tx_pin.set_high();
Timer::after(Duration::from_millis(1)).await;
tx_pin.set_high();
Timer::after(Duration::from_millis(10)).await;
info!("tick start");
// Timer::after(Duration::from_millis(100)).await;
// info!("tick end");
@@ -126,26 +126,24 @@ async fn main(spawner: Spawner) {
// yield_now().await;
let bit = rx_pin.is_high();
// info!("Rx_pin read (high): {}", bit);
// info!("Rx_pin read (high): {}", bit);
if bit as u8 != last_state {
info!(
"SW RX -> PD6 changed, new state = {}",
if bit { "HIGH" } else { "LOW" }
);
last_state = bit as u8;
continue;
yield_now().await;
}
Timer::after(Duration::from_millis(1)).await;
// ZNOVA TO ISTE ALE LOW
// ZNOVA TO ISTE ALE LOW
tx_pin.set_low();
Timer::after(Duration::from_millis(1)).await;
let low_state = rx_pin.is_high();
defmt::info!("Rx_pin (read): {}", low_state);
let n2 = PIPE_SW_RX.read(&mut buf).await;
if n2 > 0 {
info!("SW UART RX pipe: {:a}", &buf[..n2]);
}
yield_now().await;
}
}
@@ -162,6 +160,7 @@ pub async fn bridge_usart1_rx_to_usart2_tx(
let _ = usart2_tx.write(&buf[..n]).await;
info!("bridge: USART1 -> USART2 sent {} bytes", n);
}
yield_now().await;
}
}
@@ -177,5 +176,6 @@ pub async fn bridge_usart2_rx_to_usart1_tx(
let _ = usart1_tx.write(&buf[..n]).await;
info!("bridge: USART2 -> USART1 sent {} bytes", n);
}
yield_now().await;
}
}

2
semestralka_1f_rx_bez_dma_toggle/src/hw_uart_internal/driver.rs
View File

@@ -6,6 +6,7 @@ use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
use embassy_sync::pipe::Pipe;
use embedded_io_async::{Read, Write};
use crate::hw_uart_pc::safety::{RX_PIPE_CAP, TX_PIPE_CAP};
use embassy_futures::yield_now;
#[embassy_executor::task]
pub async fn uart_task(
@@ -35,5 +36,6 @@ pub async fn uart_task(
unwrap!(uart.write(&tx_buf[..n]).await);
}
}
yield_now().await;
}
}

2
semestralka_1f_rx_bez_dma_toggle/src/hw_uart_pc/driver.rs
View File

@@ -6,6 +6,7 @@ use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
use embassy_sync::pipe::Pipe;
use embedded_io_async::{Read, Write};
use crate::hw_uart_pc::safety::{RX_PIPE_CAP, TX_PIPE_CAP};
use embassy_futures::yield_now;
#[embassy_executor::task]
pub async fn uart_task(
@@ -35,5 +36,6 @@ pub async fn uart_task(
unwrap!(uart.write(&tx_buf[..n]).await);
}
}
yield_now().await;
}
}