working now pushing to the ring buffer

dma_gpio/src/software_uart/gpio_dma_uart_tx.rs

@@ -4,7 +4,7 @@ use embassy_stm32::{
     peripherals::GPDMA1_CH0,
     Peri,
 };
-use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
+use embassy_stm32::dma::WritableRingBuffer;
 
 // kapitola 17.4.11 - 2 casovace pre 2 DMA
 pub const TIM6_UP_REQ: Request = 4; // Table 137: tim6_upd_dma, strana 687 STM32U5xx datasheet
@@ -138,9 +138,10 @@ pub fn encode_uart_byte_cfg(
     idx
 }
 
-// Push UART frames for a whole byte slice into a Pipe.
-pub async fn write_uart_frames_to_pipe<const N: usize>(
-    pipe: &Pipe<CriticalSectionRawMutex, N>,
+/// Push UART frames into the DMA-backed TX ring non-blockingly.
+/// Automatically waits for free space when ring is full.
+pub async fn write_uart_frames_to_ring(
+    ring: &mut WritableRingBuffer<'static, u32>,
     pin_bit: u8,
     bytes: &[u8],
     cfg: &UartConfig,
@@ -148,21 +149,8 @@ pub async fn write_uart_frames_to_pipe<const N: usize>(
     for &b in bytes {
         let mut frame = [0u32; 12];
         let used = encode_uart_byte_cfg(pin_bit, b, cfg, &mut frame);
-        for w in &frame[..used] {
-            pipe.write(&w.to_le_bytes()).await;
-        }
-    }
-}
 
-// Optional: emit a BREAK (line LOW for 'bits' bit-times).
-pub async fn write_break_to_pipe<const N: usize>(
-    pipe: &Pipe<CriticalSectionRawMutex, N>,
-    pin_bit: u8,
-    bits: usize,
-) {
-    let set_low = |bit: u8| -> u32 { 1u32 << (bit as u32 + 16) };
-    let word = set_low(pin_bit);
-    for _ in 0..bits {
-        pipe.write(&word.to_le_bytes()).await;
+        // Will wait until all words are written
+        ring.write_exact(&frame[..used]).await.unwrap();
     }
 }

dma_gpio/src/software_uart/runtime.rs

@@ -1,16 +1,13 @@
 // src/software_uart/runtime.rs
 use embassy_executor::task;
-use embassy_stm32::pac::GPIOA;
 use embassy_stm32::{
-    peripherals::{GPDMA1_CH0, GPDMA1_CH1},
+    peripherals::GPDMA1_CH1,
     Peri,
 };
 use embassy_stm32::dma::{
     ReadableRingBuffer as DmaRingRx,
-    WritableRingBuffer as DmaRingTx,
     TransferOptions,
 };
-use crate::software_uart::gpio_dma_uart_tx::TIM6_UP_REQ;
 use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
 use crate::software_uart::gpio_dma_uart_rx::TIM7_UP_REQ;
 
@@ -37,29 +34,3 @@ pub async fn rx_dma_task(
         pipe_rx.write(&chunk).await;
     }
 }
-
-/// TX DMA ring task: streams u32 BSRR words paced by TIM6.
-#[task]
-pub async fn tx_dma_task(
-    ch: Peri<'static, GPDMA1_CH0>,
-    ring_mem: &'static mut [u32],
-) {
-    let bsrr_ptr = GPIOA.bsrr().as_ptr() as *mut u32;
-
-    let mut opts = TransferOptions::default();
-    opts.half_transfer_ir = true;
-    opts.complete_transfer_ir = true;
-
-    // SAFETY: ring_mem is exclusive here, bsrr_ptr valid, paced by TIM6
-    let mut tx = unsafe {
-        DmaRingTx::<u32>::new(ch, TIM6_UP_REQ, bsrr_ptr, ring_mem, opts)
-    };
-    
-    tx.start();
-    defmt::info!("TX DMA ring started");
-
-    // The DMA now streams ring_mem.
-    loop {
-        // embassy_futures::yield_now().await;
-    }
-}