@startuml
title TIM7 → DMA → ReadableRingBuffer → rx_dma_task

start

:TIM7 tick (oversampling);

:DMA interrupts ON;
:DMA ringbuffer setup;

repeat
  :'read_exact' cakanie na byty o velkosti CHUNK_SIZE;

  :Extract Rx z IDR → level_buf;

  :current_end = valid_len + CHUNK_SIZE;

  :Dekodovanie decode_uart_samples(level_buf[0..current_end]);

  if (decoded byty existuju?) then (ano)
    :pipe_rx.write(decoded);
  endif

  :Posunutie level_buf vlavo o 'consumed';
  :valid_len = remaining;

  if (valid_len >= HISTORY_SIZE?) then (ano)
    :Zmensenie o HISTORY_SIZE/2;
    :valid_len = HISTORY_SIZE/2;
  endif

  :yield_now();

repeat while (true)
@enduml
