// src/sleep/standby.rs

pub fn enter_standby() -> ! {
    unsafe extern "C" {
        fn HAL_PWR_EnterSTANDBYMode();
    }
    
    unsafe {
        HAL_PWR_EnterSTANDBYMode();
    }
    
    cortex_m::asm::udf(); // never happen marker
}

pub fn enter_standby_with_sram2_8kb() -> ! {
    sram2_8kb_retention();
    enter_standby();
}

pub fn enter_standby_with_sram2_full() -> ! {
    sram2_full_retention();
    enter_standby();
}

pub fn sram2_full_retention() {
    unsafe extern "C" {
        fn HAL_PWREx_EnableSRAM2ContentStandbyRetention(sram2_pages: u32);
    }

    unsafe {
        // 0x60 = PWR_SRAM2_FULL_STANDBY = PWR_CR1_RRSB1 | PWR_CR1_RRSB2
        // See: STM32U5xx HAL: stm32u5xx_hal_pwr_ex.h line 227
        // PWR_CR1_RRSB1=0x20, PWR_CR1_RRSB2=0x40
        HAL_PWREx_EnableSRAM2ContentStandbyRetention(0x60);
    }
}

pub fn sram2_8kb_retention() {
    unsafe extern "C" {
        fn HAL_PWREx_EnableSRAM2ContentStandbyRetention(sram2_pages: u32);
    }

    unsafe {
        // 0x40 = PWR_SRAM2_PAGE1_STANDBY = PWR_CR1_RRSB2
        // 8KB retention only
        HAL_PWREx_EnableSRAM2ContentStandbyRetention(0x40);
    }
}

pub fn disable_sram2_full_retention() {
    unsafe extern "C" {
        fn HAL_PWREx_DisableSRAM2ContentStandbyRetention(sram2_pages: u32);
    }

    unsafe {
        HAL_PWREx_DisableSRAM2ContentStandbyRetention(0x60);
    }
}
