-- display_drive.vhd


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity display_driver is
    Port ( 
        CLK         : in  STD_LOGIC; -- Connect to 400Hz signal
        RST         : in  STD_LOGIC;
        -- The four BCD digits from your counters
        DIGIT_0     : in  STD_LOGIC_VECTOR (3 downto 0);
        DIGIT_1     : in  STD_LOGIC_VECTOR (3 downto 0);
        DIGIT_2     : in  STD_LOGIC_VECTOR (3 downto 0);
        DIGIT_3     : in  STD_LOGIC_VECTOR (3 downto 0);
        -- Physical outputs to the FPGA pins
        SEGMENTS    : out STD_LOGIC_VECTOR (7 downto 0);
        ANODES      : out STD_LOGIC_VECTOR (3 downto 0)
    );
end display_driver;

architecture Behavioral of display_driver is
    
    component counter_2bit is
        Port ( CLK : in STD_LOGIC; RST : in STD_LOGIC; 
               COUNT_OUT : out STD_LOGIC_VECTOR (1 downto 0));
    end component;

    component decoder_an is
        Port ( SEL : in STD_LOGIC_VECTOR (1 downto 0); 
               ANODES : out STD_LOGIC_VECTOR (3 downto 0));
    end component;

    component mux is
        Port ( I0, I1, I2, I3 : in STD_LOGIC_VECTOR (3 downto 0); 
               S : in STD_LOGIC_VECTOR (1 downto 0); 
               Y : out STD_LOGIC_VECTOR (3 downto 0));
    end component;
    
    component dec_seg is
        Port ( bcd : in STD_LOGIC_VECTOR (3 downto 0); 
               seg : out STD_LOGIC_VECTOR (7 downto 0));
    end component;

    -- Internal signals stay here now
    signal s_cnt_2bit : std_logic_vector(1 downto 0);
    signal s_mux_out  : std_logic_vector(3 downto 0);
    
begin
    U_CNT_2BIT : counter_2bit
        port map (CLK => CLK, RST => RST, COUNT_OUT => s_cnt_2bit);

    U_DEC_ANODES : decoder_an
        port map (SEL => s_cnt_2bit, ANODES => ANODES);

    U_MUX : mux
        port map (I0 => DIGIT_0, I1 => DIGIT_1, I2 => DIGIT_2, I3 => DIGIT_3,
                  S  => s_cnt_2bit, Y  => s_mux_out);
        
    U_DEC_SEG : dec_seg
        port map (BCD => s_mux_out, SEG => SEGMENTS);        

end Behavioral;