flowchart LR

    %% ── Inputs ───────────────────────────────────────────────────
    CLK([CLK])
    RST([RST])
    START([START])

    %% ── Outputs ──────────────────────────────────────────────────
    SEGMENTS([SEGMENTS])
    ANODS([ANODS])

    %% ── Clock dividers ───────────────────────────────────────────
    subgraph FILE_DIV["📄 divider.vhd"]
        DIV["divider\n──────────\n100MHz → 1Hz pulse"]
    end

    subgraph FILE_DIV400["📄 divider_400Hz.vhd"]
        DIV400["divider_400Hz\n──────────\n100MHz → 400Hz pulse"]
    end

    %% ── Glue in top_modul ────────────────────────────────────────
    AND_CE(["⚡ top_modul.vhd\ns_ce_units =\nclk_1_Hz AND START"])

    %% ── BCD counter chain ────────────────────────────────────────
    subgraph FILE_CNT["📄 counter.vhd   (entity reused 4×)"]
        direction LR
        CNT_U["U_CNT_TOP\n── Units ──\nCE=s_ce_units\nTC→s_tc_units"]
        CNT_T["U_CNT_BOTTOM\n── Tens ──\nCE=s_tc_units\nTC→s_tc_tens"]
        CNT_H["U_CNT_3\n── Hundreds ──\nCE=tc_u AND tc_t\nTC→s_tc_hundreds"]
        CNT_K["U_CNT_4\n── Thousands ──\nCE=tc_u AND tc_t\n    AND tc_h\nTC=open"]

        CNT_U -->|"s_tc_units"| CNT_T
        CNT_T -->|"s_tc_tens"| CNT_H
        CNT_H -->|"s_tc_hundreds"| CNT_K
    end

    %% ── Display scan chain ───────────────────────────────────────
    subgraph FILE_CNT2["📄 counter_2bit.vhd"]
        CNT2["counter_2bit\n──────────\nIN: clk_400Hz\nOUT: s_cnt_2bit"]
    end

    subgraph FILE_DEC_AN["📄 decoder_bottom.vhd"]
        DEC_AN["decoder_an\n──────────\nIN: SEL 2-bit\nOUT: ANODES 4-bit"]
    end

    %% ── Mux + segment decode ─────────────────────────────────────
    subgraph FILE_MUX["📄 mux.vhd"]
        MUX["mux  4×4-bit\n──────────\nI0–I3: digit values\nS: s_cnt_2bit\nY: s_mux_out"]
    end

    subgraph FILE_DEC_SEG["📄 dec2.vhd"]
        DEC_SEG["dec_seg\n──────────\nBCD 4-bit\n→ SEG 8-bit"]
    end

    %% ═══════════════════════════════════════════════════════
    %% WIRING
    %% ═══════════════════════════════════════════════════════

    %% Clock sources
    CLK -->|"100 MHz"| DIV
    CLK -->|"100 MHz"| DIV400

    %% 1 Hz counting path
    DIV  -->|"clk_1_Hz"| AND_CE
    START --> AND_CE
    AND_CE -->|"s_ce_units"| CNT_U

    %% 400 Hz display scan path
    DIV400 -->|"clk_400_Hz"| CNT2
    CNT2   -->|"s_cnt_2bit"| DEC_AN
    CNT2   -->|"s_cnt_2bit (S)"| MUX
    DEC_AN -->|"ANODES"| ANODS

    %% Counter digits into mux
    CNT_U -->|"s_cnt_units  (I0)"| MUX
    CNT_T -->|"s_cnt_tens   (I1)"| MUX
    CNT_H -->|"s_cnt_hundreds (I2)"| MUX
    CNT_K -->|"s_cnt_thousands (I3)"| MUX

    %% Segment output
    MUX     -->|"s_mux_out"| DEC_SEG
    DEC_SEG -->|"SEG"| SEGMENTS