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-- Company: 
-- Engineer: 
-- 
-- Create Date: 09.03.2026 14:43:21
-- Design Name: 
-- Module Name: divider - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity divider is
    Port ( CLK : in STD_LOGIC;
           RST : in STD_LOGIC;
           CLK_1_Hz : out STD_LOGIC);
end divider;

architecture Behavioral of divider is
    -- 27 bits is enough for 100 million
    signal s_cnt : STD_LOGIC_VECTOR(26 downto 0) := (others => '0');
begin
    process(CLK)
    begin
        if rising_edge(CLK) then
            if RST = '1' then
                s_cnt <= (others => '0');
                CLK_1_Hz <= '0';
            elsif s_cnt = 99_999_999 then 
                s_cnt <= (others => '0');
                CLK_1_Hz <= '1'; -- The pulse
            else
                s_cnt <= s_cnt + 1;
                CLK_1_Hz <= '0';
            end if;
        end if;
    end process;
end Behavioral;