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-- Company: 
-- Engineer: 
-- 
-- Create Date: 09.03.2026 14:40:14
-- Design Name: 
-- Module Name: top_modul - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top_modul is
    Port ( CLK : in STD_LOGIC;
           RST : in STD_LOGIC;
           START : in STD_LOGIC;
           SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0);
           ANODS : out STD_LOGIC_VECTOR (3 downto 0));
end top_modul;

architecture Behavioral of top_modul is
    
    component divider is
        Port ( CLK : in STD_LOGIC;
               RST : in STD_LOGIC;
               CLK_1_Hz : out STD_LOGIC); -- This will be our enable pulse
    end component;
    
    component divider_400Hz is
        Port ( CLK : in STD_LOGIC;
               RST : in STD_LOGIC;
               CLK_400_Hz : out STD_LOGIC); -- This will be our enable pulse
    end component;

    signal clk_1_Hz   : std_logic;
    signal clk_400_Hz : std_logic;
    
begin

    U_DIV : divider
        port map (
            CLK => CLK,
            RST => RST,
            CLK_1_Hz => clk_1_Hz
        );
        
        
    U_DIV_400Hz : divider_400Hz
        port map (
            CLK => CLK,
            RST => RST,
            CLK_400_Hz => clk_400_Hz
        );
end Behavioral;