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-- Company: 
-- Engineer: 
-- 
-- Create Date: 23.02.2026 13:09:41
-- Design Name: 
-- Module Name: top_model - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top_model is
    Port ( SW : in STD_LOGIC_VECTOR (3 downto 0);
           ANODS : out STD_LOGIC_VECTOR (3 downto 0);
           SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0));
end top_model;

architecture Behavioral of top_model is

begin


--HEX-to-seven-segment decoder
--   HEX:   in    STD_LOGIC_VECTOR (3 downto 0);
--   LED:   out   STD_LOGIC_VECTOR (6 downto 0);
--
-- segment encoinputg
--      0
--     ---
--  5 |   | 1
--     ---   <- 6
--  4 |   | 2
--     ---
--      3

    with SW SELect
   SEGMENTS <= "01111001" when "0001",   --1
         "00100100" when "0010",   --2
         "00110000" when "0011",   --3
         "00011001" when "0100",   --4
         "00010010" when "0101",   --5
         "00000010" when "0110",   --6
         "01111000" when "0111",   --7
         "00000000" when "1000",   --8
         "00010000" when "1001",   --9
         "00001000" when "1010",   --A
         "00000011" when "1011",   --b
         "01000110" when "1100",   --C
         "00100001" when "1101",   --d
         "00000110" when "1110",   --E
         "00001110" when "1111",   --F
         "01000000" when others;   --0
   ANODS <= "1110";


end Behavioral;