
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity counter is
    Port ( CLK : in STD_LOGIC;
           DIN : in STD_LOGIC_VECTOR (3 downto 0); -- teraz nas nezaujima
           PE : in STD_LOGIC; -- teraz nas nezaujima
           CE : in STD_LOGIC;
           RST : in STD_LOGIC;
           TC : out STD_LOGIC;
           COUNT_OUT : out STD_LOGIC_VECTOR (2 downto 0));
end counter;

architecture Behavioral of counter is
    -- Internal signal to keep track of the current number
    signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := "0000";
begin

    -- Main counting logic
    process(CLK)
    begin
        if rising_edge(CLK) then
            if RST = '1' then
                s_cnt <= "0000";
            elsif CE = '1' then
                -- toto preto, lebo su to desiatky hodin, 24 hod je max, takze
                -- iba 0 - 2
                if s_cnt = "0010" then
                    s_cnt <= "0000";   -- Reset to 0
                else
                    s_cnt <= s_cnt + 1;
                end if;
            end if;
        end if;
    end process;

    -- Drive the output ports
    COUNT_OUT <= s_cnt;

end Behavioral;
