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-- Company: 
-- Engineer: 
-- 
-- Create Date: 02.03.2026 14:36:06
-- Design Name: 
-- Module Name: top_modul - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top_modul is
    Port ( CLK : in STD_LOGIC;
           RST : in STD_LOGIC;
           CE : in STD_LOGIC;
           LEDS : out STD_LOGIC_VECTOR (3 downto 0));
end top_modul;



architecture Behavioral of top_modul is


component divider is
    Port ( CLK : in STD_LOGIC;
           RST : in STD_LOGIC;
           CLK_1_Hz : out STD_LOGIC);
end component;

component counter is
    Port ( CLK : in STD_LOGIC;
           RST : in STD_LOGIC;
           CE : in std_logic;
           COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end component;

signal clk_1_hz : std_logic;
begin

divider_inst_0 : divider
   port map (
      CLK => CLK,   -- 1-bit output: Clock output
      RST => RST, -- 1-bit input: Clock enable input for I0
      CLK_1_Hz => clk_1_hz    -- 1-bit input: Primary clock
   );

counter_inst_0 : counter
    port map ( CLK => clk_1_hz,
                RST => RST,
                CE => CE,
                COUNT_OUT => LEDS
                );
                

end Behavioral;
