----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 09.03.2026 15:54:24
-- Design Name: 
-- Module Name: dec_seg - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dec_seg is
    Port ( BCD : in STD_LOGIC_VECTOR (3 downto 0);
           SEG : out STD_LOGIC_VECTOR (7 downto 0));
end dec_seg;

architecture Behavioral of dec_seg is

begin
    -- Konverzia BCD na 7-segment (ABCDEFG + DP)
    -- Formát: "ABCDEFG DP"
    
    with bcd select
        seg <= "11000000" when "0000", -- 0
               "11111001" when "0001", -- 1
               "10100100" when "0010", -- 2
               "10110000" when "0011", -- 3
               "10011001" when "0100", -- 4
               "10010010" when "0101", -- 5
               "10000010" when "0110", -- 6
               "11111000" when "0111", -- 7
               "10000000" when "1000", -- 8
               "10010000" when "1001", -- 9
               "11111111" when others; -- off

end Behavioral;
