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-- Company: 
-- Engineer: 
-- 
-- Create Date: 02.03.2026 13:52:15
-- Design Name: 
-- Module Name: divider - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity divider is
    Port ( CLK : in STD_LOGIC;
           RST : in STD_LOGIC;
           CLK_1_Hz : out STD_LOGIC);
end divider;

architecture Behavioral of divider is

signal div_cnt : STD_LOGIC_VECTOR (26 downto 0);
signal ce : STD_LOGIC;

begin

DIV: process (CLK, RST, div_cnt)
begin
    if (RST = '1') then
        div_cnt <= (others => '0');
    elsif ((CLK = '1') and (CLK'event)) then
            if (div_cnt < "0101111101011110000011111111") then
                div_cnt <= div_cnt +1;
            else
                div_cnt <= (others => '0');
            end if;
    end if;
end process;


BUFGCE_inst_0 : BUFGCE
   port map (
      O => CLK_1_Hz,   -- 1-bit output: Clock output
      CE => ce, -- 1-bit input: Clock enable input for I0
      I => CLK    -- 1-bit input: Primary clock
   );

ce <= '1' when div_cnt = "0101111101011110000011111111" 
            else '0';
   
end Behavioral;
