
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity cnt_0_5 is
    Port ( CLK : in STD_LOGIC;
           RST : in STD_LOGIC;
           CE : in STD_LOGIC;
           TC : out STD_LOGIC;
           COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end cnt_0_5;

architecture Behavioral of cnt_0_5 is
    -- Internal signal to keep track of the current number
    signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := "0000";
begin

    -- Main counting logic
    process(CLK)
    begin
        if rising_edge(CLK) then
            if RST = '1' then
                s_cnt <= "0000";
            elsif CE = '1' then
                if s_cnt = "0110" then -- If we are at 6
                    s_cnt <= "0000";   -- Reset to 0
                else
                    s_cnt <= s_cnt + 1; -- Increment
                end if;
            end if;
        end if;
    end process;

    COUNT_OUT <= s_cnt;

end Behavioral;
